Overview:
PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity.
Specifications:
Supports PCIe Gen 6 and Pipe 5.X Specifications
Core supports Flit and non-Flit Mode
Lane Configurations: X16, X8, X4, X2, X1
AXI MM and Streaming supported
Supports Gen1 to Gen6 modes
Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s
PAM support when operating at 64GT/s
Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b
Supports SerDes and non-SerDes architecture
Optional DMA support as plugin module
Support for alternate negotiation protocol
Can operate as an endpoint or root complex
Lane polarity control through register
Lane de-skew supported
Support for L1 states and L0P
Support for SKP OS add/removal and SRIS mode
No equalization support through configuration
Deemphasis negotiation support at 5GT/s
Supports EI inferences in all modes
Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
