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All IPs > Interface Controller & PHY > PCI > PCIe 6.0 PHY on 5nm

PCIe 6.0 PHY on 5nm

From Qualitas Semiconductor

Description

The Qualitas' 5nm PCIe PHY IP consists of hardmacro PMA and PCS compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power solution using 5nm FinFet CMOS technology. It includes all ESD I/Os and bump pads, and supports extensive built-in self test features such as loopback and scan.

Deliverables
Hard IP
  • GDS
  • LEF/DEF
  • Datasheet
  • Integration guide
  • Test bench
  • FE-Common: MODEL, TWRAP, TB, LEF, LIBERTY, ATPG and Platform_PSI_CMN BE-Common: CIR, GDS, DRC, LVS and DFM DOC-Common: DataSheet, UserGuide and TestGuide
Verification IP
Features
  • 5nm low power enhanced (LN05LPE) CMOS device technology
  • 1.8V±5%, 0.85V±5% dual power supply
  • Compliant to PCIe Base 6.0 and PIPE 6.1 specification
  • Support Gen1, Gen2, Gen3, Gen4, Gen5 and Gen6
  • Channel Configuration for Data Lanes
  • Common (CMN) and 1, 2 or 4 Data Lanes
  • Support the following transmitter pre-emphasis levels
  • - 3.5/-6dB for Gen1 and Gen2
  • Multi-tap FIR with resolution of 1/63 for Gen3 to Gen6
  • Support CTLE, DSP-based multi-tap FFE and 1-tap DFE for channel equalization in receiver
  • Support adaptive channel equalization
  • 100MHz reference clock is required (Support differential input buffer)
  • Built-in self test feature capable of generating and checking PRBS patterns
  • PCS included in PHY hardmacro
Foundries & Process Nodes
Foundry Process Nodes
Samsung 5nm
Tech Specs
Class Value
Categories Interface Controller & PHY > PCI
Availability All Countries & Regions
Image Gallery
PCIe 6.0 PHY on 5nm
Applications
  • Mobile
  • Automotive
  • Storage
  • AI accelerator
  • Chip-to-chip interconnect
  • etc
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