All IPs > Interface Controller & PHY > PCI > PCIe 5.0 PHY
The PCIe 5.0 PHY IP from M31 is designed for high-performance applications requiring significant data throughput. Supporting up to 32Gbps per lane, this IP is backward compatible with previous PCIe generations, offering extensive flexibility in design configuration while adhering to PIPE 5.2 specifications.
| Foundry | Process Nodes |
|---|---|
| TSMC |
10nm 22nm 28nm |
| Class | Value |
|---|---|
| Categories |
Interface Controller & PHY > PCI |
| Data Rate | 32Gbps per lane |
| Supply Voltage | 1.8V |
| Availability | All Countries & Regions |
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