The ONNC Compiler is designed to meet the growing demands of AI-on-chip development, serving as a cornerstone for transforming neural networks into machine instructions suitable for diverse processing elements. Its robust architecture supports key deep learning frameworks such as PyTorch and TensorFlow, seamlessly converting various file formats into intermediate representations using MLIR frameworks. ONNC facilitates the compilation process with advanced pre-processing capabilities powered by machine learning algorithms to convert input files optimally.
The compiler is highly versatile, supporting both single-backend and multi-backend modes to cater to different IC designs. In the single-backend mode, it generates machine instructions for general-purpose CPUs like RISC-V or domain-specific accelerators like NVDLA. For complex AI SoCs, the multi-backend mode manages resources across different processing elements, ensuring robust machine instruction streams.
ONNC's enhanced performance is achieved through hardware/software co-optimization, particularly in handling memory and bus allocations within heterogeneous multicore systems. By employing advanced techniques such as software pipelining and DMA allocation, ONNC maximizes resource utilization and curtails energy consumption without compromising on computational accuracy.
