The ONNC Compiler is a sophisticated tool designed for AI-on-chip implementations, facilitating the transformation of neural networks into machine-specific instructions. Its architecture is particularly advantageous for heterogeneous multicore SoCs, accommodating configurations like big.LITTLE ARM and various DSPs. The compiler supports a modular parser that leverages MLIR frameworks, facilitating support for popular deep learning frameworks like PyTorch and TensorFlow. It includes both single and multiple backend modes, ensuring adaptability across broad AI system-on-chip architectures, including support for PCIe accelerators and application processors in smartphones.
One of the standout features of ONNC is its capability to manage fragmented memory spaces, allowing efficient data flow and optimization across complex systems. Its design addresses intricate memory configurations with non-linear, often fragmented memory spaces, and it offers a high-dimensional memory allocation system that minimizes RAM usage. ONNC enhances performance by optimizing data movement with techniques such as software pipelining and DMA allocation, ultimately aiming to maximize processing element utilization and reduce memory overhead.
The ONNC Compiler has been engineered to be modular and retargetable, allowing it to cater to diverse hardware architectures and optimize both performance and resource use. Key optimizations such as software pipelining, DMA scheduling, and memory management support are built into its backend, making ONNC an attractive choice for those looking to maximize efficiency in AI system design.
