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All IPs > Wireline Communication > Error Correction/Detection > ntRSC_DP1.4 Display Port 1.4 Reed Solomon Codec

ntRSC_DP1.4 Display Port 1.4 Reed Solomon Codec

From Noesis Technologies P.C.

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Description

The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.

Deliverables
Soft IP
  • Compliance
  • Synthesizable RTL
  • Verilog integration testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Datasheet
  • Hardware user guide
  • Hardware implementation guide
  • Standard EDA tool flow scripts and support files
  • Verification test bench and test vectors
  • Technical support
Features
  • VESA Display Port 1.4 compliant
  • Reed Solomon RS(254,250) FEC, 10-bit symbols
  • Comprised of ntRSE_DP1.4 and ntRSD_DP1.4 Encoder and Decoder IP Cores respectively
  • Error correction performance metrics
  • Excellent error resilience performance
  • Supports error and erasure decoding
  • Single or multiple symbol rate clock
  • Predictable decoder latency
  • Fully synchronous design, using single clock
  • Silicon proven in ASIC and FPGA technologies for a variety of applications
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Class Value
Categories Wireline Communication > Error Correction/Detection
Availability All Countries & Regions
Image Gallery
ntRSC_DP1.4 Display Port 1.4 Reed Solomon Codec
Applications
  • Display Port 1.4
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