Find IP Sell IP AI Assistant Chip Talk About Us
Log In

All IPs > Wireline Communication > Error Correction/Detection > ntLDPC_WiFi6 IEEE 802.11 n/ac/ax compliant LDPC Codec

ntLDPC_WiFi6 IEEE 802.11 n/ac/ax compliant LDPC Codec

From Noesis Technologies P.C.

Description

The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.

Deliverables
Soft IP
  • Compliance
  • Synthesizable RTL
  • Verilog integration testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Datasheet
  • Hardware user guide
  • Hardware implementation guide
  • Standard EDA tool flow scripts and support files
  • Verification test bench and test vectors
Features
  • Encoder and decoder, support all IEEE 802.11 n/ac/ax defined block lengths (648, 1296, 1944) and code rates (1/2, 2/3, 3/4 and 5/6).
  • 27-Bit or 81-Bit encoder input/output interface wrappers, supporting AXI4 Lite bus protocol.
  • Soft input decoder interface wrapper with 4(S4.0), 5(S5.0, S5.1) or 6(S6.0, S6.1, S6.2) bit LLRs support and 27*LLR or 81*LLR parallelism.
  • Automatic scaling of internal fixed point precision according to selected input fixed point precision.
  • Flexible generic decoder architecture with various combinations of parallelism options providing any desired application trade-off between area, performance and throughput rates.
  • Maximum internal parallelism level of 81 parallel LLRs processing for high throughput applications.
  • Programmable Early Termination feature, with layered parity check criterion, for substantial throughput rate increase, without any measurable performance loss.
  • Probe outputs returning the number of actual performed decoding iterations per frame for quality statistics extraction.
  • Generic selection of multiple encoder/decoder instances under the same top level IO interface for seamless throughput increase.
  • Peak data rate > 4Gbps, measured on Xilinx RFSoC FPGA, with ~10% device utilization. Higher rates achievable for FPGA or ASIC technologies.
  • Synchronous single clock design.
  • Silicon proven in ASIC and Xilinx FPGA implementation technologies.
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Class Value
Categories Wireline Communication > Error Correction/Detection
Wireless Communication > 802.11
Availability All Countries & Regions
Image Gallery
ntLDPC_WiFi6 IEEE 802.11 n/ac/ax compliant LDPC Codec ntLDPC_WiFi6 IEEE 802.11 n/ac/ax compliant LDPC Codec ntLDPC_WiFi6 IEEE 802.11 n/ac/ax compliant LDPC Codec
Applications
  • IEEE 802.11 n/ac/ax Wi-Fi 4, 5 or 6 standard compliant cases.
  • Custom state-of-the-art systems for efficient high throughput FEC protection in both wireline or wireless types of applications.
Sign up to Silicon Hub to buy and sell semiconductor IP

Sign Up for Silicon Hub

Join the world's most advanced semiconductor IP marketplace!

It's free, and you'll get all the tools you need to evaluate IP, download trial versions and datasheets, and manage your evaluation workflow!

Switch to a Silicon Hub buyer account to buy semiconductor IP

Switch to a Buyer Account

To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.

Add new company

Switch to a Silicon Hub buyer account to buy semiconductor IP

Create a Buyer Account

To evaluate IP you need to be logged into a buyer profile. It's free to create a buyer profile for your company.

Loading...
Chat to Volt about this page

Chatting with Volt