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All IPs > Wireless Communication > Digital Video Broadcast > ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec

ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec

From Noesis Technologies P.C.

Description

The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation.
The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated.
The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.

Deliverables
Soft IP
  • Compliance
  • Synthesizable RTL
  • Verilog integration testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Datasheet
  • Hardware user guide
  • Hardware implementation guide
  • Standard EDA tool flow scripts and support files
  • Verification test bench and test vectors
  • Technical support
Features
  • Encoder and decoder, support all DVB S2/S2X defined block lengths 16200, 32400 and 64800.
  • Very Low SNR modes are also supported, with puncturing and shortening features implemented internally.
  • Flexible generic decoder architecture with various combinations of parallelism options providing any desired application trade-off between area, performance and throughput rates.
  • Maximum parallelism level of 360 parallel LLRs processing for high throughput applications.
  • Decoding algorithm achieves competitive performance results meeting DVB S2/S2X Quasi Error Free requirements when paired with the appropriate Noesis BCH Codec.
  • Programmable number of algorithmic iterations.
  • Programmable Early Termination feature, with convergence criterion, for substantial throughput rate increase, without measurable performance loss.
  • Probe outputs returning the number of actual performed decoding iterations per frame for quality statistics extraction.
  • 36-Bit or 360-Bit encoder input/output interface wrappers.
  • Soft input decoder interface wrapper with 5 or 6 bit LLRs support and 36*LLR or 360*LLR parallelism.
  • Synchronous single clock design.
  • Silicon proven in ASIC and Xilinx FPGA implementation technologies.
  • AXI4 Lite bus protocol support.
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Image Gallery
ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec ntLDPC_DVBS2X DVBS2/S2X compliant LDPC Codec
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