The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit.
The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure.
The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity.
The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation.
The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes.
Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
