Truechip's NoC Crossbar IP is designed to facilitate efficient chip interconnectivity by reducing latency, optimizing power use, and minimizing chip area. This IP includes a hardware cache coherency feature alongside software cache maintenance capabilities, aimed at reducing interconnecting wires and enhancing resource efficiency within chips.
Available in native Verilog, the NoC Crossbar IP ensures comprehensive test coverage through cleaned-up linting, synthesis, and CDC/RDC processes. Each IP is rigorously verified by experts using detailed regression test suites, ensuring reliability. The IP's integration is simplified with a GUI tool, accompanied by detailed documentation and unique licensing models.
Key features include support for a range of protocols such as AMBA AXI, AHB, and APB, with configurable memory maps for diverse memory region access. The IP supports variable data widths and includes mechanisms for early response and interrupt generation, arbitration modes, and clock gating. These features ensure that the NoC Crossbar IP is a valuable asset for both ASIC and SoC environments.
