Truechip's NoC Crossbar Silicon IP is designed to facilitate the connection of multiple devices supporting various protocol buses. By implementing a crossbar network, this IP seamlessly reduces latency and power consumption while maintaining low area usage in a design. It effectively enhances hardware and software cache coherency and significantly reduces the need for interconnecting wires, hence conserving chip resources.
The NoC Crossbar Silicon IP is available in a native Verilog RTL, ensuring clean linting, synthesis, CDC, and RDC processes. Truechip backs its IP with thorough verification by an expert team utilizing comprehensive regression test suites. Consistency in interface, installation, operational procedures, and documentation ensures a smooth integration between the IP and existing systems. The IP provides ease of use through a GUI-based integration and configuration tool, backed by reliable 24X5 customer support.
It supports multiple levels of interconnection with several master and slave ports, allowing for highly customizable configurations. Various protocols can be supported across individual ports, and data-width can vary to meet specific design requirements. Features like QoS support, back-to-back transfers, and different phase-shifted frequencies further bolster its performance in a network-on-chip design.
