The NoC Coherent Crossbar IP from Truechip delivers an efficient interconnect solution that supports multi-protocol devices with minimal latency and optimal power and area usage. The IP integrates hardware cache coherency to ensure efficient data management and reduced interconnect resource utilization within the chip.
Packaged in native Verilog, the IP ensures full code coverage and quality assurance through extensive regression testing. It provides a straightforward interface for integration and configuration through a user-friendly GUI tool and comes with extensive documentation for seamless adoption.
The IP supports a variety of protocols such as AMBA CHI and AXI, with both full and non-coherent node configurations. Other features include configurable arbitration modes, clock gating, and support for both little and big endianness, making this IP suitable for complex chip designs requiring flexible data interfacing and management solutions.
