Overview:
The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses.
Key Features:
Compliance with JEDEC's JESD300-5
Support for speeds up to 12.5MHz
Bus Reset functionality
SDA arbitration support
Enabled Parity Check
Support for Packet Error Check (PEC)
Switch between I2C and I3C Basic Mode
Default Read address pointer Mode
Write and read operations for SPD5 Hub with or without PEC
In-band Interrupt (IBI) support
Write Protection for NVM memory blocks
Arbitration for Interrupts
Clearing of Device Status and IBI Status Registers
Error handling for Packet Error Check and Parity Errors
Common Command Codes (CCC) for I3C Basic Mode
Dynamic IO Operation Mode Switching
Bus Clear and Bus Reset capabilities
SPD5 Command features for NVM memory and Register Space
Read and Write access to NVM memory
Support for Offline Tester operation
Applications:
DDR5 DIMM Application Environment
DDR5 NVDIMM Application Environment
Automotive Devices
Memory Devices
Power Management Devices
Defense/Aerospace/Customer Electronics
