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All IPs > Interface Controller & PHY > MIPI > MIPI-I3C Combo Host/Target (Master/Slave) HDR-DDR

MIPI-I3C Combo Host/Target (Master/Slave) HDR-DDR

From MAXVY Technologies Pvt Ltd

Description

MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs).

The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system.

The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus.

The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration.

MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.

Features
  • Two wire serial interface up to 12.5MHz using Push-Pull.
  • Compliance as per MIPI-I3C Basic v1.1.1
  • Backward compatibility with I2C.
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices.
  • Support Single Data Rate messaging(SDR).
  • Supports Broadcast and Direct Common Command Code (CCC) Messages.
  • In-Band Interrupt (IBI)
  • Hot-Join Support.
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Class Value
Categories Interface Controller & PHY > MIPI
Compliant Standard MIPI-I3C Basic v1.1.1
Maturity silicon proven ip
FPGA I3C HOST/TARGET FPGA READY Test Environment
Availability All Countries & Regions
Applications
  • Consumer Electronics
  • Defense
  • Aerospace
  • Virtual Reality
  • Augmented Reality
  • Medical
  • Biometrics
  • Automotive Devices
  • Sensor Devices
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