Overview:
The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices.
Key Features:
Compliance with MIPI-DSI-2 version 2.0
Compliance with C-PHY version 2.0 for DSI-2 Version-2
Compliance with D-PHY version 1.2 for DSI-2 Version-2.0
Compliance with D-PHY version 2.0 for DSI-2 Version-2.0
Compliance with D-PHY version 3.0 for DSI-2 Version-2.0
Compliance with MIPI SDF specification
Compliance with DBI-2 and DPI-2
Pixel to Byte conversion support from Application layer to LLP layer
Support for Command Mode and Video Mode
Continuous clock behavior in clock lane for D-PHY physical layer
De-skew sequence pattern for video mode support
Lane Distribution Function for distributing packet bytes across N-Lanes
Connectivity with two, three, or four DSI Receivers
HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY
Symbol slip detection code and sync symbol insertion in C-PHY physical layer
Target Applications:
Imaging
Surveillance
Gaming
Sensor devices
Internet of Things (IoT)
Wearable devices
Virtual Reality
Augmented Reality
Automotive Systems
