All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
The CT25205 is a sophisticated digital controller designed for 10BASE-T1S Ethernet communications. Compatible with IEEE 802.3cg, it integrates the PMA, PCS, and PLCA Reconciliation sublayers, making it highly suitable for standard cells and FPGA systems. This synthesizable IP core supports seamless integration into any standard IEEE CSMA/CD Clause 4 Ethernet MAC via MII, which enhances its versatility for a multitude of applications. Its embedded PLCA RS uniquely allows existing MAC implementations to adopt advanced PLCA capabilities effortlessly, ensuring an increase in functionality without hardware overhauls. In conjunction with other Canova Tech IPs, such as the CT25208 MAC controller and CT25210 topology discovery IP, it provides a complete solution for implementing 10BASE-T1S within Zonal Gateways System on Chips (SoCs) and microcontrollers. The amalgamation of these components offers a streamlined approach to developing efficient network communication protocols, paving the way for innovative uses in industrial and automotive sectors where reliable data transmission is critical. This IP is especially adept at working alongside standard OPEN Alliance 10BASE-T1S PMD interfaces, reinforcing its compatibility with established industry protocols. For those developing multi-drop Ethernet solutions, the CT25205 stands as a premier choice. Its design, which ensures adherence to IEEE standards while promoting enhanced reliability and performance, makes it an attractive option for a range of applications, from simplifying connectivity in industrial setups to fortifying communications in vehicular networks, underscoring Canova Tech’s commitment to technological advancement and innovation.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Eliyan's NuLink Die-to-Die PHY technology represents a significant advancement in chiplet interconnect solutions. Designed for standard packaging, this innovative PHY IP delivers robust high-performance with low power consumption, a balance that is crucial for modern semiconductor designs. The NuLink PHY supports multiple industry standards, including the Universal Chiplet Interface Express (UCIe) and Bunch of Wires (BoW), ensuring it can cater to a wide range of applications. A standout feature of the NuLink PHY is its simultaneous bidirectional (SBD) signaling capability, which allows data to be sent and received over the same wire at the same time, effectively doubling bandwidth. This makes it an ideal solution for data-intensive applications such as AI training and inference, particularly those requiring ultra-low latency and high reliability. The technology is also adaptable for different substrates, including both silicon and organic, offering designers flexibility in their packaging approaches. NuLink's architecture stems from extensive industry insights and is informed by Eliyan’s commitment to innovation. The platform provides a power-efficient and cost-effective alternative to traditional advanced packaging solutions. It achieves interposer-like performance metrics without the complexity and cost associated with such methods, enabling operational efficiency and reduced time-to-market for new semiconductor products.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Time-Triggered Ethernet is a specialized communication protocol developed to incorporate the deterministic properties of traditional time-triggered systems within the robust and widely used Ethernet networking technology. It serves industries that require high precision and reliable data transmissions, like aerospace and automotive systems, where safety is paramount and timing is critical. This protocol extends conventional Ethernet by adding timestamping and scheduling features, enabling precise control over data transmission times. By doing so, it ensures that data packets are transmitted predictably within fixed timeslots, providing a network solution that combines the widespread adoption of Ethernet with high determinism demands. Time-Triggered Ethernet thus bridges the gap between standard Ethernet's flexibility and the strict timing requirements of critical systems. Applications of Time-Triggered Ethernet span from integrating advanced avionics systems to enabling reliable communication in autonomous vehicle networks. Its design supports modularity and scalability, allowing it to adapt as systems become more complex or requirements change, without sacrificing the precise timing and reliability essential for real-time communications in critical applications.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The MIPITM CSI2MUX-A1F is an innovative video multiplexor designed to manage and aggregate multiple video streams effortlessly. It supports CSI2 rev 1.3 and DPHY rev 1.2 standards, handling inputs from up to four CSI2 cameras and producing a single aggregated video output. With data rates of 4 x 1.5Gbps, it is optimal for applications requiring efficient video stream management and consolidation.
The MIPI DSI-2 Transmitter IP from Arasan is engineered for streamlined communication between processors and display panels, a critical component in the rapidly evolving displays of mobile devices. Aligning with the MIPI DSI standards, this Transmitter IP ensures interoperability and high-speed data transmission, achieving the requisite performance for vivid and responsive displays. Key attributes include multi-lane data handling, reduced data transmission latency, and comprehensive support for various display configurations and modes. Arasan's DSI-2 Transmitter is optimized for power efficiency, employing techniques like low-power modes and clock gating to curtail power consumption and extend device battery life. Customers benefit from Arasan's extensive experience and support throughout the integration process, ensuring a robust, reliable, and compliant display solution that meets the needs of next-generation mobile applications.
This engine features ultra-low latency FPGA IP, providing a robust TCP Offload in networking systems. The integration includes MAC, PCIe, and Host Interface, ensuring sector-leading performance with minimal latency. Built on a background of efficient data transfer protocols, the system enhances throughput while reducing CPU overhead, which is particularly advantageous for high-frequency trading or real-time applications. Characterized by its ultra-low latency capabilities, the IP facilitates enhanced data handling that allows for immediate processing, making it ideal for data-heavy environments like data centers and financial services. The integration of a MAC interface alongside PCIe provides a cohesive solution that rapidly processes network traffic, addressing both data-heavy and computationally demanding tasks. Designed for environments demanding reduced latency, this IP underscores Intilop's commitment to cutting-edge data solutions. It accommodates concurrent sessions with high-speed data throughputs, thereby minimizing the computational load on conventional processing units and achieving execution speeds that are unparalleled in the market.
The GNSS VHDL Library from GNSS Sensor Ltd is designed to streamline satellite navigation system integration into FPGA platforms. This versatile library includes numerous modules such as configurable GNSS engines and fast search engines catering to GPS, GLONASS, and Galileo systems. Complementing these are special components like a Viterbi decoder and RF front-end control, ensuring comprehensive system integration support. Engineered to achieve maximum independence from CPU platforms, the GNSS VHDL Library is built upon a simple configuration file to deliver flexibility and ease of use. Users benefit from pre-built FPGA images compatible with both 32-bit SPARC-V8 and 64-bit RISC-V architectures. The library enables GNSS operations as a co-processor with SPI interface, supporting diverse external bus interfaces without requiring changes in the core library structure. The GNSS VHDL Library incorporates Simplified Core Bus (SCB) for interfacing, enabling interactions through a system-defined bridge module. This provides flexibility in design and ensures efficient data processing and integration with existing systems, simplifying the development process for both new and existing FPGA platforms. Whether enhancing current designs or developing new navigation solutions, this library equips developers with the tools needed for effective GPS, GLONASS, and Galileo integration.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The BlueLynx Chiplet Interconnect facilitates seamless communication between chiplets, vital for modern semiconductor designs that emphasize modularity and efficiency. This technology supports both physical and link layer interfaces, adhering to the Universal Chiplet Interconnect Express (UCIe) and Open Compute Project (OCP) Bunch of Wires (BoW) standards. BlueLynx ensures high-speed data transfer, offering customizable options to tailor designs for specific workloads and application needs. Optimized for AI, high-performance computing, and mobile markets, BlueLynx's die-to-die adaptability provides system architects with the leeway to integrate a variety of packaging types and process nodes, including 2D, advanced 2.5D, and innovative 3D packaging options. The solution is recognized for delivering a balance of bandwidth, energy efficiency, and latency, ensuring robust system performance while minimizing power consumption. This IP has been silicon-proven across multiple process nodes, including advanced technologies like 3nm, 4nm, and 5nm, and is supported by major semiconductor foundries. It offers valuable features such as low latency, improved PPA (Power, Performance, Area), and industry-standard compliance, positioning it as a reliable and high-performing interconnect solution within the semiconductor industry.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The SerDes (Serializer/Deserializer) PHY offered by Terminus Circuits represents an integral component essential for various data communication technologies, where heightened bandwidth and speed are critical. This technology is crafted to accommodate diverse nodes, multiple foundries, and protocols, ensuring their solutions meet even the most demanding customer requirements. Features include low power consumption, minimal latency, and compact physical design, setting it apart for users demanding efficient SerDes technology. Terminus Circuits provides a comprehensive set of deliverables for their SerDes PHY, including user guides for integration, meticulous timing libraries, and Verilog code. This solution is adaptable to a broad spectrum of market segments, encompassing sectors like network communication, data storage, and enterprise networking, thanks to its seamless interoperability with existing controllers. With the ability to support diverse protocols such as PCI Express, USB 3.1, and various optical interfaces, the SerDes PHY provides an essential backbone for robust high-speed data exchange. The SerDes PHY is particularly noted for its capacity to handle conventional as well as emerging networking and storage protocols, with configurations that support variations across different data rates and standards. Such versatility in supporting bifurcation modes and progressive equalization techniques ensures optimal signal integrity and minimized data latency, catering to sophisticated applications requiring high-speed, reliable data transfer.
The MIPI (Mobile Industry Processor Interface) offered by Silicon Library is a high-performance interface designed to connect various semiconductor components. Featuring both DPHY-Tx and DPHY-Rx configurations, it supports a multitude of applications that require efficient data transfer This interface is particularly adept at supporting camera and display connections within mobile devices. Its low-power architecture extends battery life, making it an ideal choice for smartphones and tablet PCs. MIPI ensures streamlined data pathways, crucial for the fluid operation of camera sensors and display screens. With its ability to support a wide range of data speeds, MIPI serves as the backbone for many of the mobile industry's leading technologies, enhancing communication between chips and ensuring that data is moved quickly and reliably. Its standardization and versatility make it a favored choice in the development of high-performance mobile devices.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
With an emphasis on performance, the MIPITM SVTPlus2500 is a robust 4-lane video transmitter adhering to CSI2 rev 2.0 and DPHY rev 1.2 standards. It facilitates timing closure with its low clock rating and supports PRBS for precise data management. The transmitter can handle 8/16 pixel inputs per clock and offers programmable timing parameters. Equipped with 16 virtual channels, this IP is engineered for high-speed video transmission.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
In the realm of smartphones, ActLight introduces its Dynamic PhotoDetector (DPD) technology, which significantly optimizes various aspects of phone functionality. The integration of DPD in smartphone applications, such as proximity sensing, ambient light detection, and 3D sensing, paves the way for enhanced user interactions and efficient operation. This sensor technology uses advanced 3D Time-of-Flight (ToF) camera technology to ensure precise detection and measurement of light intensity for a variety of uses. By delivering high sensitivity to even the smallest changes in light, ActLight's DPD transforms how smartphones manage power efficiency, allowing for better battery conservation. Its low-voltage operation reduces overall power consumption, a crucial factor in mobile devices that need to maintain long battery life for uninterrupted use. Moreover, the DPD technology enables new functionalities such as enhanced eye-tracking for augmented and virtual reality, providing insights into user behavior and improving the immersive experience. In addition to gaming and media, these advancements support the evolving needs of data-driven applications and interactive consumer technologies.
Analog Bits' I/O solutions are engineered to provide high-quality signaling between integrated circuits, supporting a variety of applications with unparalleled efficiency. These I/Os are optimized for low power consumption and high performance, designed to meet the stringent demands of state-of-the-art electronic devices. The wide array of I/O solutions is tailored to support die-to-die communications with minimal power loss, ensuring swift data exchange processes. These I/O products are implemented on advanced process nodes, guaranteeing their effectiveness in modern semiconductor environments. The expertise of Analog Bits in crafting these solutions ensures that they are highly customizable, adapting seamlessly to diverse client requirements and thereby offering significant improvements in design flexibility. Silicon-proven and trusted across leading foundries, these I/O solutions are at the heart of high-volume semiconductor production. They are particularly effective in applications that demand precise signal transmission and reception, underscoring their vital role in facilitating reliable chip-to-chip communication in various high-tech industries.
The second-generation MIPITM SVRPlus-8L-F is a high performance serial video receiver built for FPGAs. Complying with CSI2 revision 2.0 and DPHY revision 1.2 standards, it supports 8 lanes and 16 virtual channels, offering efficient communication with 12Gbps data throughput. This receiver comes with features like 4 pixel output per clock, calibration support, and communication error statistics, making it suitable for high-speed video transmission and processing applications.
The MIPI D-PHY from SkyeChip is a thoroughly integrated macro designed to comply with the MIPI D-PHY v2.5 specification. With capabilities of up to 1.5 Gbps per lane and optional upgrades to 2.5 Gbps, it supports various low-power escape modes and ultra low-power states. This feature set is strategically designed for applications needing flexible high-speed data transfer capabilities.
Brite Semiconductor's YouMIPI offers a complete set of solutions for MIPI interfaces, particularly focusing on the CSI and DSI standards. The solution is adept at handling data from a sensor to the image processing parts of a system, converting byte streams into pixel data while mitigating electromagnetic interference through configurable data scrambling. Featuring compliance with multiple versions of the MIPI standards, YouMIPI supports substantial data rates across several lanes in C-PHY and D-PHY configurations, allowing for flexible integration with a wide range of application processors. The architecture provides efficient multi-channel distribution and manages synchronization effortlessly, addressing both high-speed and low-power operational modes as specified by MIPI. YouMIPI is particularly designed for use in camera modules and display interfaces in mobile devices, automotive solutions, and consumer electronics. The robust design underpinning YouMIPI ensures optimal data handling and high-quality signal processing for superior image and display performance.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The Chipchain C100 is a sophisticated, single-chip solution designed for Internet of Things (IoT) applications. It is built around a 32-bit RISC-V CPU operating at speeds of up to 1.5GHz, supplemented by embedded RAM and ROM, ensuring exceptional computational efficiency. The C100 integrates several essential features for IoT use, including Wi-Fi capability, multiple data transmission interfaces, and built-in ADCs, LDOs, and temperature sensors. This integration is aimed at simplifying and expediting application development across various domains ranging from security to healthcare.
SystemBIST is an advanced product offering from Intellitech that provides a plug-and-play solution for flexible FPGA configuration and embedded JTAG testing. It stands out with its proprietary architecture that allows for efficient, codeless configuration of field-programmable gate arrays (FPGAs) as well as built-in system testing capabilities. SystemBIST is designed to be vendor-neutral, supporting any FPGA or CPLD compliant with the IEEE 1532 or IEEE 1149.1 standards. This design enables robust anti-tamper measures and enhances system reliability by embedding JTAG test patterns directly into PCBs.
The Time-Triggered Protocol (TTP) is an advanced communication protocol designed for highly reliable and deterministic networks, primarily utilized in the aerospace and automotive sectors. It provides a framework for the synchronized execution of tasks within a network, facilitating precise timing and coordination. By ensuring that data transmission occurs at predetermined times, TTP enhances the predictiveness and reliability of network operations, making it vital for safety-critical applications. The protocol is engineered to function in environments where reliability and determinism are non-negotiable, offering robust fault-tolerance and scalability. This makes it particularly suited for complex systems such as those found in avionics, where precise timing and synchronization are crucial. The design of TTP allows for easy integration and scalability, providing flexibility that can accommodate evolving system requirements or new technological advancements. Moreover, TTP is characterized by its rigorous adherence to real-time communication standards, enabling seamless integration across various platforms. Its deterministic nature ensures that network communications are predictable and maintain high standards of safety and fault tolerance. These features are crucial in maintaining operational integrity in critical applications like aerospace and automotive systems.
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
Arasan's MIPI CSI-2 Receiver IP facilitates seamless integration between cameras and host processors in a plethora of devices, providing high-speed data transfer crucial for modern imaging systems. This IP adheres to the latest MIPI CSI specifications, ensuring compatibility and high performance across a range of camera modules. The CSI-2 Receiver IP boasts features such as multi-lane support, dynamic pixel format compatibility, and error handling mechanisms that ensure reliable data communication. In addition to its compliance and interoperability, this IP is designed to optimize power consumption, featuring advanced low-power modes and clock gating techniques to extend battery life in mobile applications. By choosing Arasan's CSI-2 Receiver IP, developers receive a fully verified solution supported by an industry leader, tailored to meet the increasing demands of high-resolution imaging systems in mobile platforms.
The MIPITM SVTPlus-8L-F is a cutting-edge serial video transmitter designed for FPGAs. This transmitter adheres to CSI2 rev 2.0 and DPHY rev 1.2, featuring 8 lanes and capable of handling data rates of up to 12Gbps. It's engineered for high-performance video applications, boasting robust processing capabilities. Its support for advanced transmission protocols ensures seamless integration and compatibility with a wide range of video systems.
The Catalyst-GbE provides high-performance networking solutions for PXIe systems, equipped to handle intensive data transmission tasks efficiently. Featuring state-of-the-art COTS NIC modules, it delivers superior Ethernet connectivity by leveraging Intel and NVIDIA Mellanox technology. Designed to operate within a single-slot PXIe/CPCIe configuration, Catalyst-GbE modules provide exceptional value and performance for PXIe systems, achieving rapid deployment with their 30-day delivery window. Their modularity makes them suitable for a range of tasks, ensuring seamless integration into existing systems while offering excellent pricing and value in the marketplace. By facilitating robust Ethernet connectivity, the Catalyst-GbE enhances networking capabilities within PXIe platforms, fitting perfectly for applications needing multiple high-speed data lanes like test and measurement and rapid data processing setups.
The MIPI C-PHY interface is designed to enhance bandwidth efficiency for the MIPI CSI-2 protocol, providing a data transfer rate of 5.7Gbps per lane. This interface is pivotal for applications demanding higher throughput without the need to increase signaling clocks. By improving data transmission efficiency, it serves critical needs in areas like mobile and augmented reality devices, where effective data handling is crucial to performance.
The HUMMINGBIRD is an advanced Optical Network-on-Chip (NoC), designed to optimize data flow within complex computing environments. By integrating photonic networking capabilities, HUMMINGBIRD allows for streamlined data communication across chip components, reducing latency and power use significantly. Its architecture is geared towards accommodating rapid, efficient data processing, proving essential for data centers aiming to enhance internal communication without the bottleneck of traditional electronic interconnections. As an embodiment of optical advancements, HUMMINGBIRD sets the stage for enhanced computational harmony and performance.
The Nerve IIoT Platform by TTTech Industrial Automation is a sophisticated edge computing solution that bridges the gap between industrial environments and digital business models. Designed for machine builders, it supports real-time data exchange, offering a robust infrastructure that connects physical machines directly with IT systems. The platform optimizes machine performance by allowing for remote management and software deployment. Nerve's architecture is highly modular, making it adaptable to specific industrial needs. It features cloud-managed services that enable seamless application deployments across multiple devices, straight from the cloud or on-premises infrastructure. By supporting various hardware, from simple gateways to industrial PCs, the platform is scalable and capable of growing with business demands. Security is a pivotal aspect of Nerve, offering both IEC 62443 certification for safe deployment and regular penetration tests to ensure integrity and protection. Its integration capabilities with protocols like OPC UA, MQTT, and others allow for enhanced data collection and real-time analytics, promoting efficiency and reducing operational costs through predictive maintenance and system optimization.
The DisplayPort 1.4 core offers a comprehensive solution for DisplayPort-based designs, supporting both source (DPTX) and sink (DPRX) functionalities. It accommodates various link rates including 1.62, 2.7, 5.4, and 8.1 Gbps, as well as eDP rates, providing flexibility for different applications. The IP infrastructure supports 1, 2, and 4 DP lanes, making it suitable for various display configurations. Featuring native video and AXI stream interfaces, the core efficiently manages video streams with single and multi-stream transport modes. It handles dual and quad pixels per clock alongside support for 8 & 10-bit video in both RGB and YUV color spaces. This versatility ensures that designers can integrate the IP into a multitude of systems, ensuring high compatibility and performance. Additionally, the core is bundled with a Video Toolbox for specific video processing tasks, which include timing and test pattern generation as well as video clock recovery. A sleek host driver and API facilitate its integration and control, while support for a wide array of FPGA devices, including AMD and Intel's leading technologies, ensures flexibility in its deployment.
The MIPI IP from XtremeSilica supports the development of camera and display modules in today's interconnected devices. This flexible interface caters to various media and communication applications, ensuring data is transmitted accurately and swiftly between components. The MIPI IP facilitates high-bandwidth data transfer with low power consumption, essential for battery-operated devices where efficiency is key. Its broad compatibility helps manufacturers innovate across different product lines, from smartphones to wearables, without sacrificing quality or performance. This IP provides scalable benefits, allowing easy adaptation to evolving device capabilities. It is crucial in optimizing design footprints and ensuring reliable, quick data exchanges, ultimately leading to superior end-user experiences.
The MIPI CSI-2 Tx Compact Transmitter is a versatile module designed to transmit high-speed image data efficiently between camera and associated systems, crucial for imaging and video processing applications. It is compatible with several FPGA platforms, including Xilinx Spartan-6/7, Kintex, Zynq, Ultrascale, and Ultrascale+, providing operational flexibility across different hardware setups. This transmitter facilitates the seamless integration of camera solutions into complex multimedia systems, ensuring high-quality image transmission with minimal latency. Its design is optimized for compact implementation, making it ideal for applications where space and efficiency are paramount. The transmitter also supports a range of process nodes across different foundries, enhancing its adaptability to various manufacturing criteria. Technical support is streamlined through its wide adoption in industries, making it a reliable choice for entities looking to implement cutting-edge video technology. As a component of BitsimNOW's suite of IP products, this transmitter exemplifies the company's commitment to providing advanced solutions for high-performance video data handling.
This high-speed interface product is designed to accommodate data rates up to 12.5Gbps, providing exceptional performance for connecting digital-to-analog converters, among other uses. It supports the JESD204B standard for serial data interconnect, ensuring reliable data transfer with features including deterministic latency support and comprehensive SYSREF functionality. The design incorporates independent transmitting and receiving blocks capable of handling complex data flows, such as 8b/10b encoding and scrambling. Engineered for versatility, the IP core allows for flexible data packet and lane width configurations. This adaptability makes it suitable for a wide range of applications in radio frequency (RF) communications and high-speed data acquisition systems. Furthermore, the product's support for various foundry process nodes, including 65nm, 55nm, 40nm, and 28nm, enhances its usability across different manufacturing environments. These technical specifications make it an essential component for developers seeking efficient interconnect solutions in advanced electronics and communications systems.
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