All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
WAVE6 represents the pinnacle of multi-standard video coding. It supports AV1 encoding, known for its efficient use of bandwidth and high compression quality. Featuring a simple architecture, it boasts a single-clock domain that synchronizes the entropy and video codec engines on the fly. The efficiency of WAVE6 is further enhanced by its power-efficient design, which minimizes consumer energy requirements through effective clock gating. It serves various sectors, including data centers and surveillance systems, operating with a remarkable performance of up to 8K60fps @ 1GHz. The integration of advanced coding techniques ensures a reduced need for external memory, thanks to the proprietary CFrame lossless compression.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The CT25205 Digital IP core is engineered to provide the core building blocks for 10BASE-T1S Ethernet applications, including PMA, PCS, and PLCA Reconciliation Sublayer adherence. Written in Verilog 2005 HDL, it is fully synthesizable with standard cells and FPGA, working cohesively with standard IEEE CSMA/CD Ethernet MAC via MII. The unit supports advanced PLCA features, enabling seamless communication with existing MAC devices. Connectivity is ensured through a standard OPEN Alliance 10BASE-T1S PMD Interface, creating an optimal solution for Zonal Gateway SoCs and MCUs adopting innovative 10BASE-T1S communication.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinix’s commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The Trion FPGA family by Efinix addresses the dynamic needs of edge computing and IoT applications. These devices range from 4K to 120K logic elements, balancing computational capability with efficient power usage for a wide range of general-purpose applications. Trion FPGAs are designed to empower edge devices with rapid processing capabilities and flexible interfacing. They support a diverse array of use-cases, from industrial automation systems to consumable electronics requiring enhanced connectivity and real-time data processing. Offering a pragmatic solution for designers, Trion FPGAs integrate seamlessly into existing systems, facilitating swift development and deployment. They provide unparalleled adaptability to meet the intricate demands of modern technological environments, thereby enabling innovative edge and IoT solutions to flourish.
Building on its predecessor, the WAVE5 series offers robust multi-standard video encoding capabilities with an established reputation within media and entertainment sectors. WAVE5 is versatile, boasting formats like HEVC and AVC, and delivers outstanding performance, with outputs like 4K240fps at 1GHz. It has been fine-tuned to handle complex multi-instance operations by efficiently managing data transfer and conversion tasks. Its ability to maintain high visual fidelity while offering low installation costs makes it a strategic choice for multiple application fields such as automotive and mobile entertainment. The use of secondary AXI ports and a fully integrated rotation and scaling mechanic add to its versatility.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MIPITM CSI2MUX-A1F stands as a formidable CSI2 Video Multiplexor, crafted to manage inputs from multiple cameras, aggregating them into a single enhanced video stream. Compatible with CSI2 rev 1.3 and DPHY rev 1.2 protocols, it boasts the ability to handle input from up to four CSI2 cameras, funneling this data into a unified, high-quality video output. This multiplexor excels in consolidating various video inputs, making it an optimal choice for systems necessitating centralized video management. With a capacity of 4 x 1.5Gbps, it ensures there is no compromise on video quality or frame rate, maintaining high fidelity throughout the transmission. Offering an effective solution for video intensive applications, the MIPITM CSI2MUX-A1F reflects VLSI Plus Ltd.’s commitment to delivering reliable and high-performance multiplexer solutions. It provides a streamlined approach to handling video inputs, supporting applications where space and efficiency are paramount.
SkyeChip’s MIPI D-PHY is a fully integrated interface solution adhering to the MIPI D-PHY v2.5 standard. This IP block supports data transfer rates up to 1.5 Gbps per lane, extendable to 2.5 Gbps per lane for enhanced throughput. Its low-power state modes make it highly efficient for portable and low-energy system designs. By offering seamless lane control and interface logic integration, it caters to various demanding connectivity specifications, ensuring compatibility and efficiency in data transmission applications.
Silicon Library's MIPI IP is crafted to meet the stringent requirements of modern mobile and multimedia applications. It includes D-PHY transmitter and receiver components, which are essential for high-speed data communication between components like cameras, displays, and processors within portable devices. The MIPI D-PHY IP is compliant with the latest MIPI standards, ensuring smooth data flow and reducing electromagnetic interference, critical for maintaining data integrity. Its applications span a range of sectors, from mobile phones to tablets and automotive systems, where high-performance data transmission is essential. This IP's design emphasizes low power consumption and efficient data handling, making it ideal for use in energy-sensitive devices. Furthermore, it supports a variety of video resolutions and data rates, providing flexibility in designing multimedia devices.
Efinix's Topaz FPGA series is engineered for mass-market applications, delivering a perfect mix of efficiency and adaptability. These FPGAs encapsulate a highly efficient architecture, combined with the industry's essential features and protocols, such as PCIe Gen3, MIPI, and LPDDR4. This configuration allows users to harness substantial performance while maintaining ample room for future innovations. Topaz FPGAs are optimized for high-volume production environments where cost-effectiveness and swift integration are paramount. Their design promotes ease of implementation in various applications, spanning from automotive to deeply embedded systems, where reliability and robustness are key. Featuring a streamlined architecture, Topaz series FPGAs support modern connectivity standards and data processing capabilities. These devices are tailored for industries requiring scalable solutions that can adapt to evolving technological landscapes, ensuring that Efinix customers remain competitive in their respective fields.
Dream Chip Technologies' Arria 10 System on Module (SoM) emphasizes embedded and automotive vision applications. Utilizing Altera's Arria 10 SoC Devices, the SoM is compact yet packed with powerful capabilities. It features a dual-core Cortex A9 CPU and supports up to 480 KLEs of FPGA logic elements, providing ample space for customization and processing tasks. The module integrates robust power management features to ensure efficient energy usage, with interfaces for DDR4 memory, PCIe Gen3, Ethernet, and 12G SDI among others, housed in a form factor measuring just 8 cm by 6.5 cm. Engineered to support high-speed data processing, the Arria 10 SoM includes dual DDR4 memory interfaces and 12 transceivers at 12 Gbit/s and above. It provides comprehensive connectivity options, including two USB ports, Gigabit Ethernet, and multiple GPIOs with level-shifting capabilities. This level of integration makes it optimal for developing solutions for automotive systems, particularly in scenarios requiring high-speed data and image processing. Additionally, the SoM comes with a suite of reference designs, such as the Intel Arria 10 Golden System Reference Design, to expedite development cycles. This includes pre-configured HPS and memory controller IP, as well as customized U-Boot and Angström Linux distributions, further enriching its utility in automotive and embedded domains.
Mobiveil's NVM Express Controller is engineered to maximize the potential of PCIe-based SSDs across enterprise and consumer devices. It is specifically designed to support multi-core architectures which benefit from efficient queue management and interrupt handling. The controller's architecture is optimized to enhance link utilization, reduce latency, and ensure reliable and efficient operation, making it an ideal fit for high-performance and mission-critical applications.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Designed for efficient video reception, the MIPITM SVRPlus2500 is a 4-lane video receiver defined by its adherence to CSI2 rev 2.0 and DPHY rev 1.2 standards. It is characterized by its low clock rating, which significantly eases timing closure, ensuring seamless operation in real-time video applications. This receiver also incorporates PRBS support, enhancing its functionality for a wide range of video data processing tasks. The advanced design of the MIPITM SVRPlus2500 allows it to output 4, 8, or 16 pixels per clock, providing flexibility for different application requirements. With calibration support and a 1:16 input deserializers feature per lane, it efficiently manages video streams across 16 virtual channels. Additionally, its high transfer rate of 4 x 2.5Gbps caters to demanding video data environments. This video receiver is ideal for applications where high data throughput and multiple data lane handling are critical. It offers reliability and efficiency, reflecting VLSI Plus Ltd.'s commitment to providing robust and scalable video technology solutions.
Analog Bits offers a diverse range of low-power I/O solutions designed to accommodate die-to-die communication needs. These solutions are silicon-proven at 5nm and are in the process of being adapted to 3nm technologies. They feature differential clocking and signaling with crystal oscillators, tailored to provide the highest signaling quality using the fewest transistors. As designed by a reputable company, these customizable IPs are available in high-volume production, backed by support from leading fabs and foundries. Ideal for various semiconductor applications, the I/O solutions provide flexibility and reliability.
The MIPI C-PHY Interface offers a physical channel for the Camera Serial Interface 2 (CSI-2), providing a bandwidth of 5.7 Gbps per lane. By optimizing throughput over channels limited by bandwidth, this technology facilitates increased data transmission without demanding a higher signaling clock rate, making it highly efficient for next-gen applications.
The MIPITM SVRPlus-8L-F is engineered as a cutting-edge serial video receiver tailored for FPGAs, offering extensive capabilities with its 8-lane configuration and high data throughput. Adhering to the CSI2 rev 2.0 and DPHY rev 1.2 standards, it supports up to 16 virtual channels and allows for output of up to 4 pixels per clock. Additional functionalities include calibration support and comprehensive communication error statistics, providing users with a robust solution for video transfer applications. This receiver is particularly suitable for high-demand environments where efficient data processing and the management of multiple data streams are essential. Its high-speed capabilities are underscored by a remarkable 12Gbps data transfer rate, ensuring smooth and effective video transmission without bottlenecking the system. The MIPITM SVRPlus-8L-F is thus ideal for applications necessitating real-time video handling and processing. As a feature-rich component, the MIPITM SVRPlus-8L-F exemplifies the sophisticated design principles synonymous with VLSI Plus Ltd. Its readiness for immediate deployment, alongside established standards compatibility, establishes it as a preferred choice in professional video handling and transport solutions.
The MIPITM SVTPlus-8L-F is a high-performance serial video transmitter designed for integration with FPGAs. This transmitter stands out for its 8-lane architecture, enabling it to adhere strictly to the CSI2 rev 2.0 and DPHY rev 1.2 specifications. Supporting high-speed data transfer rates of up to 12Gbps, it ensures that large volumes of video data are transmitted efficiently and without delay, making it an excellent choice for video-centric applications. Built to support high throughput, the MIPITM SVTPlus-8L-F is tailored for environments that require reliable and swift transmission of video data over serial links. Its features highlight the capacity to manage intensive video data streams, providing an edge where time-sensitive data transmission is paramount. The transmitter exhibits a robust design that accommodates diverse environments, offering flexibility and reliability. Ensuring seamless integration into varied applications, the MIPITM SVTPlus-8L-F is engineered to meet the ever-evolving demands of video data handling and processing. Its ability to handle complex video data efficiently positions it as a valuable asset in applications requiring heightened data transmission speeds and operational stability.
Arasan's MIPI DSI-2 Transmitter IP provides a high-performance, scalable solution for enhancing display interfaces in mobile applications. Compliant with the latest MIPI DSI standards, this IP enables efficient data transmission between processors and display panels, suited for high-resolution, power-sensitive environments. It's geared to support the stringent demands of today’s advanced display technologies, offering flexibility across multiple DSI configurations while ensuring minimal power draw. The DSI-2 Transmitter IP supports advanced features such as multiple data lane configurations, seamless color depth adjustments, and adaptive resolution management, which are crucial for achieving stellar visual outputs in mobile and embedded devices. Built with an emphasis on signal integrity and performance, it supports a wide range of data rates, making it versatile for different display panel technologies. With a focus on compliance and interoperability, the DSI-2 Transmitter assures seamless integration with various D-PHY configurations, facilitating efficient design rollouts and reducing time to market. Its architecture supports error correction and synchronization, ensuring data integrity and reliability, a crucial aspect when dealing with high resolutions and demanding visualization requirements.
Eliyan's NuLink Die-to-Die PHY for standard packaging is a technological innovation designed to enhance chiplet interconnectivity within conventional package forms. Tailored to seamlessly integrate with both silicon bridges and organic package substrates, this product eliminates the need for advanced packaging solutions while matching their performance characteristics. By achieving the same remarkable levels of data transfer efficiency and power optimization typically associated with advanced methods, NuLink technology stands out as a cost-effective solution for multi-die integration. Targeted for ASIC designs, the NuLink Die-to-Die PHY is capable of supporting a wide array of industry standards including UCIe and BoW. Its design enables the connection of chiplets in standard packaging without requiring large silicon interposers, ensuring both significant performance gains and cost savings. This flexibility makes it particularly appealing for systems that require mixing and matching of chiplets of varying dimensions. In practical applications, Eliyan’s solution facilitates increased placement flexibility and supports configurations that demand physical separation of components, such as those between hot ASICs and heat-sensitive dies. By leveraging a standard packaging approach, this PHY product provides substantial improvements in thermal management, cost efficiency, and production timelines compared to traditional methods.
The xSPI MRAM product family from Everspin is crafted for Industrial IoT and embedded systems, using their proprietary STT MRAM technology. These devices adapt the Expanded Serial Peripheral Interface standard, offering high-speed, low pin count communication with a frequency up to 200 MHz. Operating on a single 1.8V supply, xSPI MRAMs deliver a throughput up to 400MBps, perfect for applications replacing legacy SRAMs, NVSRAMs, or NOR Flash. This range targets diverse sectors including automotive, gaming, and industrial automation.
The MIPITM SVTPlus2500 is a state-of-the-art 4-lane video transmitter fitted for applications demanding high-speed video data transmission. Complying with the latest CSI2 rev 2.0 and DPHY rev 1.2 standards, it supports a seamless operation with programmable timing parameters, ensuring optimal synchronization and data integrity. One of the key attributes of the MIPITM SVTPlus2500 is its PRBS support for error handling and data validation, alongside the ability to manage 8 or 16 pixels per clock. This is complemented by a flexible low clock rating to simplify timing closure, enhancing its appeal for complex data processing tasks. The transmitter's capability to handle multiple data lanes allows for scalability in advanced video transmission systems. With a supported rate of 4 x 2.5Gbps, the MIPITM SVTPlus2500 caters to scenarios where precise video data transmission is required, offering a robust yet adaptable solution. This product illustrates VLSI Plus Ltd.'s expertise in designing IP cores that support high-bandwidth video communication.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
SystemBIST represents a comprehensive plug-and-play device enhancing FPGA configurations and embedded JTAG testing methodologies on PCBs. This sophisticated module allows for seamless FPGA device programming and reconfiguration in-field, supporting IEEE 1532 and IEEE 1149.1 standards. Designed with a vendor-independent approach, SystemBIST offers scalable configurations for both flash memory and CPLD devices, integrating built-in self-tests (BIST) that utilize stored test patterns in flash memory. This product simplifies the traditional complex methods of FPGA configuration, removing the need for large PROM parts and streamlining production concerns with its cost-effective design, widening its appeal across sectors needing flexible, reliable re-programmable solutions.
YouMIPI offers a comprehensive array of solutions designed to support the MIPI interface standards, including both CSI and DSI protocols. These solutions are instrumental in managing video and imaging data transmission, a critical requirement for modern mobile and embedded systems. The focus on high-performance and low-energy dissipation ensures that the YouMIPI suite upholds quality and efficiency in visual data handling. The CSI interface facilitates the handling of camera data streams seamlessly, ensuring that image data is processed with minimal latency and maximum quality retention. Similarly, the DSI interface addresses the demands of display data transmission, optimizing for both bandwidth and energy consumption to ensure optimum performance. Ideal for both developers of mobile devices and embedded systems, the YouMIPI solutions prioritize integration flexibility and performance enhancement. Their design integrates seamlessly into a wide range of products, from smartphones to smart devices, ensuring high-quality visual data processing and display capabilities.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
The BlueLynx Chiplet Interconnect offers an advanced die-to-die interconnect solution, tailored to meet the rigorous demands of contemporary chiplet designs. With support for Universal Chiplet Interconnect Express (UCIe) and the Open Compute Project's Bunch of Wires (BoW), this IP establishes a robust physical and link layer interface for chiplet communications. It's built to connect efficiently with on-die bus standards like AMBA AXI and ACE, streamlining the process of linking chiplets within advanced package configurations. Technologically sophisticated, BlueLynx supports a variety of fabrication nodes ranging from 16nm down to 3nm, ensuring compatibility across multiple semiconductor foundries. This interconnect solution is silicon-proven and enables not only rapid development but also minimizes the traditional risks associated with new designs. Clients receive a comprehensive ASIC integration package, including platform software and design references, which allows for swift silicon bring-up and ensures that first-pass silicon achieves expected operational standards. The architecture of BlueLynx is designed to be both customizable and efficient. With data rates stretching from 2 Gb/s up to over 40 Gb/s, and low power consumption underpinning its design, BlueLynx manages to provide a high bandwidth density of over 15 Tbps/mm². This results in optimal performance scaling across diverse applications while accommodating advanced 3D packaging options. The PHY component of the IP is specifically designed for high compatibility and minimal latency, built on the architecture that supports configurable serialization and deserialization ratios, multiple PHY slices, along with detailed specifications for bump pitch and package applications.
Tentiva is Parretto's versatile Video FMC board designed to enhance video processing with a high degree of modularity. It boasts two modular PHY slots enabling seamless customization and expansion, supporting up to 20 Gbps data rates. These slots serve as a high-speed channel between the Tentiva board and connected PHY cards. Suitable for a range of applications, Tentiva supports multiple PHY cards including DPT14X for DisplayPort 1.4 transmission, and DP21RX for reception, among others. This high level of adaptability means it's a robust choice for flexible video processing setups. Engineered to integrate smoothly with FPGA development boards that feature FMC headers, Tentiva offers broad compatibility with different manufacturers' hardware. Its flexible architecture makes it ideal for a wide range of video applications, demanding both performance and adaptability.
The MIPI CSI-2 Tx Compact Transmitter is a streamlined solution designed for the Xilinx Spartan-6/7, Kintex, Zynq, Ultrascale, and Ultrascale+ platforms, as well as Intel Cyclone 10 LP MAX10 and Microsemi PolarFire. This innovative product targets the efficient transmission of video data from various sources adhering to the MIPI CSI-2 standard. The transmitter significantly cuts down latency, ensuring the reliable delivery of high-speed data streams, which is crucial for real-time applications in imaging and video processing.
The C100 represents an advanced integration of wireless microcontroller capabilities for Internet of Things (IoT) applications. Built around a powerful 32-bit RISC-V CPU operating at speeds up to 1.5GHz, this chip delivers high-efficiency processing and data handling. Embedded with RAM and ROM, the C100 is designed to maintain high performance while minimizing power usage. Complementing its processing power, the C100 integrates extensively with wireless functionalities including Wi-Fi, and supports a multitude of transmission interfaces. Additionally, it includes an Analog-to-Digital Converter (ADC), Low Dropout Regulator (LDO), and a temperature sensor, allowing it to cater to diverse application needs swiftly and efficiently. Its design seeks to offer seamless application development that is broad in range yet simple and fast, making it a perfect choice for developers focused on creating robust IoT solutions. The C100's strength lies not just in its integrated components but also in its ability to adapt to secure, high-performance environments, making it useful for smart home systems, healthcare devices, and more.
The CoaXPress IP by EASii IC delivers high-speed imaging solutions, accommodating applications in industrial vision, medical imaging, and broadcast. By leveraging traditional coaxial cable simplicity combined with advanced serial data technology, CoaXPress provides a unique solution for high-speed imaging and data transmission. The technology supports multi-link, multi-stream capabilities, allowing significant data throughput, up to 100 Gbps, via multiple concurrent connections. Designed to be compliant with the CoaXPress 1.1.1 and 2.0 standards, the IP offers dynamic reconfiguration during operation and supports a host of connection topologies, ensuring a flexible and high-performing infrastructure.
The MIPI CSI-2 Receiver IP by Arasan facilitates seamless integration of camera sensors with host processors, designed to support a spectrum of image formats and high bandwidth data transfer. It adheres to the latest CSI-2 standard, ensuring compatibility with a wide range of devices and delivering efficient image data processing for applications ranging from smartphones to advanced drones. Its architecture is optimized for low power consumption, making it ideal for battery-operated devices while maintaining high performance and speed in image data handling. This IP handles operations such as image frame capturing, data synchronization, and error detection, supporting both D-PHY and C-PHY latest configurations. It ensures minimal latency and lossless data transfer, which is crucial for high-resolution image capturing. Through its robust design, Arasan's CSI-2 Receiver supports up to 4 data lanes at a maximum bandwidth, thereby facilitating high-speed image data throughput that caters to modern market needs. Its compliance with the MIPI CSI-2 specification ensures it meets rigorous industry standards, providing users with reliable and interoperable solutions. Additionally, it offers features such as adaptive lane management and error correction to enhance system robustness and reliability, making it a trusted component in enhancing imaging capabilities.
This compact receiver by BitSim NOW is designed to interface with a range of FPGA platforms like Xilinx Spartan-6/7, Kintex, Zynq, Ultrascale, and Ultrascale+ as well as Intel Cyclone 10 LP MAX10 and Microsemi PolarFire. The product efficiently decodes video data conforming to the MIPI CSI-2 specification. It plays a crucial role in video data acquisition, supporting the precise synchronization and handling of high-resolution video streams. Its compact design ensures it fits well into space-constrained environments without compromising performance.
The ARINC 818 IP Core is designed to facilitate advanced digital video transport over fiber optics, commonly used in avionics for cockpit displays. This IP core ensures precise and reliable video data transmission, adhering to the ARINC 818 protocol standard. The technology is scalable and adaptable to various data formats, enabling seamless integration into existing systems.
The GNSS VHDL Library from GNSS Sensor Ltd is designed to streamline satellite navigation system integration into FPGA platforms. This versatile library includes numerous modules such as configurable GNSS engines and fast search engines catering to GPS, GLONASS, and Galileo systems. Complementing these are special components like a Viterbi decoder and RF front-end control, ensuring comprehensive system integration support. Engineered to achieve maximum independence from CPU platforms, the GNSS VHDL Library is built upon a simple configuration file to deliver flexibility and ease of use. Users benefit from pre-built FPGA images compatible with both 32-bit SPARC-V8 and 64-bit RISC-V architectures. The library enables GNSS operations as a co-processor with SPI interface, supporting diverse external bus interfaces without requiring changes in the core library structure. The GNSS VHDL Library incorporates Simplified Core Bus (SCB) for interfacing, enabling interactions through a system-defined bridge module. This provides flexibility in design and ensures efficient data processing and integration with existing systems, simplifying the development process for both new and existing FPGA platforms. Whether enhancing current designs or developing new navigation solutions, this library equips developers with the tools needed for effective GPS, GLONASS, and Galileo integration.
The SerDes offering from KNiulink is engineered to meet the demanding requirements of bandwidth-heavy applications. It supports a variety of protocols including PCI Express, Rapid IO, SATA/SAS, JESD204, and USB interface standards. With support for up to 112G, this high-speed receiver-transceiver solution incorporates advanced techniques to optimize both power efficiency and signal integrity. It's specifically tailored for applications requiring reduced power consumption without sacrificing data throughput, making it an ideal choice for data centers, communication networks, and AI applications. The flexibility of the SerDes architecture allows it to be configured according to specific customer requirements, facilitating seamless integration into logic circuits and larger System on Chip (SoC) designs. This adaptability is complemented by cutting-edge CMOS technology which further enhances its performance metrics. SerDes is integral to the creation of high-performance virtual and physical environments, ensuring future-proof scalability with low latency and high reliability. Engineered for superior configurability and performance, KNiulink's SerDes ensures that high-speed communication can be managed effectively even in the most challenging environments, offering solutions that are tailored to bridge the gap between current needs and future technological developments.
Arasan's MIPI D-PHY Analog Transceiver is engineered to facilitate high-speed data communication between camera sensors and processors or display interfaces. Supporting both CSI-2 and DSI protocols, this transceiver ensures efficient, high-capacity data transmission with minimal power consumption. Compliant with the MIPI D-PHY specification, this IP component can function as a standalone transmitter, receiver, or complete transceiver, offering robust signal integrity for diverse multimedia applications. Capable of adapting various data rates and signaling methods, the D-PHY Transceiver is a versatile solution for manufacturers targeting mobile and automotive markets. Its architecture is optimized to handle high-speed, low-latency communication, critical for applications like modern smartphones and autonomous vehicles that demand near-instantaneous data exchange. The transceiver’s design supports multiple data lanes, configurable PLL, and integrated digital interface, which simplifies implementation in complex SoC designs. By ensuring compliance with multiple MIPI specifications, Arasan’s D-PHY Transceiver minimizes development risk and facilitates faster product rollouts.