All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The SerDes Interfaces developed by Silicon Creations are optimized for high-speed serial data links, processing speeds up to 32.75Gbps across various protocols. These interfaces provide exceptional flexibility and feature rich configurability to align with specific customer needs in advanced data transmission environments. With PMAs optimized for ultra-low latency and reduced area footprint, the SerDes interfaces demonstrate high efficiency and performance. Leveraging Silicon Creations’ ring PLL technology, these interfaces ensure the delivery of reliable and precise data communication capabilities, pivotal for next-generation electronic solutions.
LVDS Interfaces by Silicon Creations are designed to facilitate high-speed and reliable data transmission. These interfaces are suitable for applications requiring efficient chip-to-chip communication, handling data rates up to 3.3Gbps. Featuring bi-directional capabilities and superb programmability, they can support a variety of standards and are engineered to deliver optimal signal integrity. Silicon Creations' use of robust PLLs and adaptive CDR technologies ensures the interfaces provide stable and precise alignment across all lanes. The impressive flexibility and performance of these interfaces make them ideal for a wide spectrum of modern digital applications.
The Connected Vehicle Solutions by KPIT focus on integrating in-vehicle systems with the broader connected world, transforming the cockpit experience. Utilizing high-resolution displays, augmented reality, and AI-driven personalization, these solutions improve productivity, safety, and user engagement. The company's advancements in over-the-air updates facilitate seamless vehicle interactions and connectivity, ushering in new revenue streams for OEMs while overcoming the challenges of system integration and market competitiveness.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
WAVE6 is a sophisticated multi-standard video codec designed to handle an array of video standards such as AV1, HEVC, AVC, and VP9. Capable of efficiently managing high-resolution video encoding and decoding processes, WAVE6 offers unmatched performance for applications demanding 4K and 8K resolutions. The technology incorporates a dual-core architecture that doubles operational efficiency and is crucial for high-throughput sectors like data centers and surveillance systems. Key features include support for color depth adaptations ranging from 8-bit to 10-bit and advanced power efficiency mechanisms. The WAVE6 codec is notable for incorporating features such as Chips&Media’s unique lossless frame buffer compression technology, CFrame™, to significantly minimize external memory bandwidth usage. With a streamlined architecture that simplifies video processing tasks, this codec supports multiple interface standards, enhancing your system's scalability and integration. High versatility makes WAVE6 a preferred choice for modern multimedia processing units, providing effective solutions for bandwidth challenges while maintaining superior image quality. WAVE6's efficient resource management and multi-instance capabilities make it a standout product in environments requiring low power consumption and high output precision. It facilitates color space conversion, bit-depth switching, and offers secondary interface options, tailoring it for a diverse range of implementation scenarios, from mobile technology to media broadcasting facilities.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The AI Camera Module from Altek is an innovative integration of image sensor technology and intelligent processing, designed to cater to the burgeoning needs of AI in imaging. It combines rich optical design capabilities with software-hardware amalgamation competencies, delivering multiple AI camera models that assist clients in achieving differentiated AI + IoT needs. This flexible camera module excels in edge computing by supporting high-resolution requirements such as 2K and 4K, thereby becoming an indispensable tool in environments demanding detailed image analysis. The AI Camera Module allows for superior adaptability in performing functions such as facial detection and edge computation, thus broadening its applicability across industries. Altek's collaboration with major global brands fortifies the AI Camera Module's position in the market, ensuring it meets diverse client specifications. Whether used in security, industrial, or home automation applications, this module effectively integrates into various systems to deliver enhanced visual processing capabilities.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The CT25205 integrates several building blocks of the IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. Designed with Verilog HDL, this digital core is optimized for implementation on both standard cells and FPGA architectures, ensuring seamless compatibility with IEEE Ethernet MAC interfaces through MII. The core's standout feature is the integrated Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer, which allows existing MACs to leverage PLCA benefits without additional hardware modifications. A key aspect of this design is its connectivity to an OPEN Alliance 10BASE-T1S PMD Interface, streamlining integration into Zonal Gateways and MCUs. Paired with Canova Tech's complementary IPs, such as the CT25208 MAC controller, CT25205 forms the backbone of cutting-edge communication systems in industries requiring efficient data exchange. The CT25205 supports a wide array of industrial applications due to its robustness and capability to enhance the existing communication frameworks. It is particularly well-suited for automotive and industrial environments where reliable and durable Ethernet solutions are crucial.
SkyeChip’s MIPI D-PHY is a fully integrated interface solution adhering to the MIPI D-PHY v2.5 standard. This IP block supports data transfer rates up to 1.5 Gbps per lane, extendable to 2.5 Gbps per lane for enhanced throughput. Its low-power state modes make it highly efficient for portable and low-energy system designs. By offering seamless lane control and interface logic integration, it caters to various demanding connectivity specifications, ensuring compatibility and efficiency in data transmission applications.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The MIPITM CSI2MUX-A1F operates as a sophisticated CSI2 video multiplexor designed to handle multiple camera inputs simultaneously. In compliance with CSI2 rev 1.3 and DPHY rev 1.2 standards, this multiplexor can manage inputs from up to four CSI2 cameras, consolidating them into a single comprehensive video stream. Engineered for high-efficiency video streamlining, it operates at a data rate of 4 x 1.5Gbps, ensuring real-time processing and efficient data throughput. The ability to integrate multiple video feeds into a single output makes it suitable for systems requiring complex multimedia handling and advanced video applications. This multiplexor provides solutions for systems where video data from various sources needs to be aggregated efficiently, optimizing space and resource utilization across video interfaces. Its seamless integration expands its utility across multiple paradigms, making it a staple in any comprehensive video system architecture.
Mobiveil's NVM Express Controller is engineered to unlock the full potential of PCIe-based SSDs within both enterprise and client platforms. It leverages a sophisticated architecture to maximize link utilization, throughput, and reliability while minimizing latency and power consumption. The controller supports multi-core configurations without locking threads, ensuring efficient operation across varied computing environments, from enterprise data centers to client-based applications.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MIPI DSI-2 Transmitter IP from Arasan Chip Systems caters to the requirement for high-performance display interfaces in mobile and automotive environments. This IP core is designed to support the MIPI DSI standard, facilitating seamless connectivity with high-resolution displays and ensuring optimally bright and vibrant image outputs in devices. Offering a scalable architecture, the DSI-2 Transmitter IP is ideal for integrating with a variety of display panels. Its design ensures low latency and efficient data throughput, benefiting devices that demand high-speed graphical data processing. The IP is also optimized for low power consumption, making it suitable for portable electronics that require extended battery life. The IP's robust support for a variety of video formats makes it an ideal solution for diverse applications ranging from consumer electronics to infotainment systems in vehicles. It further supports advanced capabilities such as video compression and error correction, ensuring consistent and high-quality visual performance.
The MIPITM SVRPlus-8L-F is an advanced 8-lane second-generation serial video receiver tailored for FPGA applications. It adheres to the CSI2 rev 2.0 and DPHY rev 1.2 standards, featuring an impressive ability to handle 16 virtual channels and output 4 pixels per clock. The receiver boasts a robust calibration support mechanism coupled with comprehensive communication error statistics, making it an optimal choice for high-performance video applications. Operating at a substantial data rate of 12Gbps, the IP is designed to meet the high demands of modern video systems. Its integration ease and high functionality are supported by its detailed error-reporting capabilities, which provide invaluable insights for system improvements. This IP's architecture is ideal for ensuring seamless video data reception, maintaining integrity, and optimizing performance. Further enhancing its effectiveness, the MIPITM SVRPlus-8L-F is equipped with calibration support, offering a complete package for efficient and reliable video signal processing in varied environments.
WAVE5 is a mature multi-standard video codec IP designed to meet the demands of high-performance multimedia processing. Supporting AV1, HEVC, AVC, and VP9 decoding, WAVE5 delivers exceptional speed and efficiency, making it suitable for various applications including data centers, surveillance, and set-top boxes. This codec achieves stunning high-resolution performance with 4K and 8K video streams, providing a comprehensive suite of virtualization and encoding tools that maximize resource utility. The WAVE5 architecture is optimized for both power and bandwidth efficiency, thanks to its dual-core setup and state-of-the-art clock gating techniques. It supports extensive pixel depth options and advanced features such as multi-instance support and frame buffer compression. This can considerably reduce latency while simultaneously optimizing image quality across diverse platforms. Applications that require reliable, high-speed video processing benefit greatly from WAVE5’s dependable multi-format compatibility and robust interface options. Equipped with extensive video formatting options and features, WAVE5 allows color format conversions, deep pixel manipulations, and effective data handling functionalities. These features create a seamless operation for developers aiming to integrate high-performing video codec solutions with broad compatibility across modern video standards.
The MIPITM SVRPlus2500 is an efficiently designed 4-lane video receiver that meets the challenges of contemporary video systems through its compliance with CSI2 rev 2.0 and DPHY rev 1.2 standards. This device is crafted for high-performance applications, featuring a low clock rating that facilitates easy timing closure and supports PRBS. Capable of handling 4/8/16 output pixels per clock, this receiver includes innovative calibration support and 1:16 input deserializers per lane. Its 16 virtual channels empower it to manage robust data streams, operating effectively at a data throughput of 4 x 2.5Gbps, which ensures high fidelity in video reception. The SVRPlus2500 stands as a versatile solution for diverse video processing needs, balancing performance and integration with ease. Its reliability in managing high data rates and providing seamless video reception makes it ideal for a wide array of advanced video applications.
Designed for FPGA contexts, the MIPITM SVTPlus-8L-F is a sophisticated 8-lane second-generation serial video transmitter. Adhering to the stringent requirements of the CSI2 rev 2.0 and DPHY rev 1.2 standards, this transmitter delivers data at an impressive 12Gbps. It stands out for its seamless integration into video systems, offering unparalleled data transmission capabilities and upholding the fidelity of transmitted signals. The transmitter is designed to support high data loads, ensuring that it can handle intensive video applications with ease. Its design not only facilitates robust data rates but also ensures that the transmitted signals maintain clarity and accuracy, essential for advanced video processing systems. By incorporating modern design methodologies, the MIPITM SVTPlus-8L-F ensures reliable data flow, minimal transmission errors, and enhanced system performance. This transmitter is a pivotal addition to any advanced digital video system, providing essential high-speed data transmission features.
The Arria 10 System on Module (SoM) is designed with a focus on embedded and automotive vision applications, leveraging the robust capabilities of the Arria 10 SoC devices. Packed in a compact form factor of 8 cm by 6.5 cm, this module incorporates a multitude of interfaces, offering immense flexibility and a wide array of functionalities suitable for high-performance tasks. This SoM integrates an Altera Arria 10 FPGA with 160 to 480 KLEs along with a Cortex A9 Dual Core CPU, ensuring efficient computational performance. It features a sophisticated power management system and support for dual DDR4 memory interfaces, optimizing power distribution and memory efficiency for safety-critical applications which demand precision and reliability. The Arria 10 SoM is crafted to maximize data throughput, with capabilities such as PCIe Gen3 x8 and 10/40 GBit/s Ethernet interfaces, alongside dedicated clocking arrangements for minimized jitter. Supporting high-speed data transmissions via multiple LVDS lanes and USB interfaces, it's engineered to handle demanding operations in sophisticated systems requiring rapid processing speeds and expansive interfacing.
The MIPI C-PHY Interface offers a physical channel for the Camera Serial Interface 2 (CSI-2), providing a bandwidth of 5.7 Gbps per lane. By optimizing throughput over channels limited by bandwidth, this technology facilitates increased data transmission without demanding a higher signaling clock rate, making it highly efficient for next-gen applications.
The YouMIPI solution is tailored for seamless integration of MIPI CSI and DSI interfaces. Brite's solution manages sensor data conversion to imagery format, along with configurable noise reduction features to minimize EMI impacts. Compliance with the latest MIPI CSI and DSI standards ensures broad application compatibility, supporting multiple image formats for diverse visualization applications. This comprehensive solution focuses on maintaining data integrity while overcoming typical signal interference challenges in high-speed transmission environments.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Suited for high throughput applications, the MIPITM SVTPlus2500 is a versatile 4-lane video transmitter compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards. This transmitter offers seamless operation with a low clock rating, simplifying timing closure challenges, and supports PRBS and calibration for enhanced accuracy. It is designed to handle 8/16 pixel inputs per clock, offering programmable timing parameters for versatile use across different systems. With its capacity to manage 16 virtual channels and achieve data rates up to 4 x 2.5Gbps, it ensures efficient video signal transmission with minimal data loss. The SVTPlus2500's adaptability makes it ideal for sophisticated video systems, offering controlled and precise data transmission over flexible configurations. Its robust system integration capabilities are designed to meet a broad range of industry standards, enhancing overall operational efficiency.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
BitSim NOW's MIPI CSI-2 Rx Compact Receiver is designed to deliver high-performance data reception for imaging and graphical applications. This receiver is compatible with FPGA platforms such as Xilinx Spartan-6/7, Kintex, Zynq, and Ultrascale series, ensuring a wide compatibility range for developers and engineers. By supporting high-speed data reception, the Rx Compact Receiver facilitates seamless communication and data integrity, which are essential in real-time imaging processes and applications that require precise data management. The receiver is engineered to support robust data handling capabilities, enhancing the overall system efficiency.
The MIPI CSI-2 Tx Compact Transmitter designed by BitSim NOW is a versatile solution for transmitting data efficiently across different platforms. It is compatible with Xilinx Spartan-6/7, Kintex, Zynq, Ultrascale, and Ultrascale+ platforms, making it suitable for a wide range of applications in imaging and graphics. This transmitter ensures reliable data transfer and optimal performance across various devices, enhancing the capability of integrated systems. It facilitates high-speed communication channels which are critical in applications requiring rapid data processing and low latency.
Eliyan’s NuLink technology revolutionizes die-to-die connections in the semiconductor landscape by delivering robust performance and energy efficiency using industry-standard packaging. The NuLink PHY is designed to optimize serial high-speed die-to-die links, accommodating custom and standard interconnect schemes like UCIe and BoW. It achieves significant benchmarks in terms of power efficiency, bandwidth, and scalability, providing the same benefits typical of advanced packaging techniques but within a standard packaging framework. This versatility enables broader cost-effective solutions by circumventing the high cost and complexity often associated with silicon interposers. NuLink Die-to-Die PHY stands out for its integration flexibility, supporting both silicon and organic substrate environments while maintaining superior data throughput and minimal latency. This innovation is particularly beneficial for system architects aiming to maximize performance within chiplet-based architectures, allowing the strategic incorporation of elements such as high-bandwidth memory and silicon photonics. NuLink further advances system integration by enabling simultaneous bidirectional signaling (SBD), doubling the effective data bandwidth on the same interface line. This singular feature is pivotal for intensive processing applications like AI and machine learning, where robust and rapid data interchange is critical. Eliyan’s NuLink can be implemented in diverse application scenarios, showcasing its ability to manage large-scale, multi-die integrations without the customary bottlenecks of area and mechanical structure. By leading system designs away from vendor-specific, cost-prohibitive supply chains, Eliyan empowers designers with increased freedom and efficiency, further underpinning its groundbreaking role in die-to-die connectivity and beyond.
SystemBIST is a revolutionary product within Intellitech’s IP portfolio, providing unparalleled capabilities for FPGA configuration and JTAG-based embedded testing. As a flexible plug-and-play device, SystemBIST allows the configuration of a wide range of IEEE 1532 or IEEE 1149.1 compliant FPGAs and CPLDs. This makes it highly versatile for design engineers looking to develop high-quality, self-testable products that can be reconfigured in the field, extending product life and adaptability. Built on patented architectures, SystemBIST simplifies typical configuration challenges by embedding built-in self-test (BIST) capabilities, thereby eliminating the need for complex software-driven BIT solutions. This device effectively compresses and stores test patterns and scripts within FLASH memory, allowing for comprehensive PCB testing wherever power is available. SystemBIST caters to a broad spectrum of applications, from normal operation reconfigurations to safe field updates, ensuring that the underlying firmware remains secure against potential threats like trojan bitstreams. Its user-friendly development tools facilitate rapid deployment and debugging, offering developers an efficient means of maintaining system integrity and performance over time.
The BlueLynx Chiplet Interconnect represents a pivotal development in die-to-die communication, emphasizing versatility through support for both the Universal Chiplet Interconnect Express (UCIe) and the Open Compute Project's Bunch of Wires (BoW) standards. This innovative solution is designed to integrate smoothly with on-die buses and Networks-on-Chip (NoCs), accommodating a variety of protocols such as AMBA, AXI, and ACE. This product is optimized for high-bandwidth applications, addressing the stringent power, performance, and area (PPA) requirements of modern chip designs. By utilizing a dual-mode PHY and offering extensive configurability in data rates and packaging options, the BlueLynx interconnect facilitates rapid, efficient system integration. Silicon-proven across numerous process nodes, including advanced nodes like 3nm and 4nm, BlueLynx is tailored to meet the diverse needs of the semiconductor market. Its customizable architecture ensures that each implementation maximizes bandwidth and minimizes power usage, supporting complex systems with ease.
Arasan's MIPI CSI-2 Receiver IP is designed to meet the needs of modern image processing applications. This IP core facilitates the integration of high-resolution cameras by supporting advanced MIPI protocols compliant with the latest standards. It offers versatile data formats and high data throughput capabilities, essential for applications in smartphones, tablets, and other mobile devices. Leveraging a robust architecture, the CSI-2 Receiver IP enhances data integrity and transmission efficiency. Its low power consumption and compact design are tailored for space-constrained environments in consumer electronics and automotive sectors. Advanced error correction features ensure reliability and robustness, critical for real-time video processing and streaming applications. The IP supports a wide range of MIPI protocol features, offering designers flexibility and scalability. Its integration ease ensures that product design cycles are shortened, enabling quicker time-to-market for innovative new products. As such, Arasan's MIPI CSI-2 Receiver IP is a preferred choice for engineers seeking high-performance, dependable camera interface solutions.
MIPI IP from Silicon Library is engineered for high-speed, low-power data transmission in mobile devices. By supporting MIPI Alliance standards, this IP ensures compatibility and seamless operation with numerous types of sensors and displays, which is crucial in the production of mobile phones, tablets, and lightweight digital gadgets. This MIPI IP solution includes D-PHY modules, which cater to both the transmission (Tx) and reception (Rx) of data. It operates across multiple data lanes, offering flexibility and scalability to brands aiming to enhance their mobile hardware capabilities. With extensive compatibility across DSI and CSI interfaces, the MIPI IP ensures efficient signal integrity and low electromagnetic interference, critical for compact electronic designs. With an impressive range of data rates supported, from low power to high speed modes, the MIPI IP is built to accommodate the increased demands of processing extensive data in modern smart devices. Its energy-efficient design is specifically optimized to prolong battery life without compromising on data throughput or reliability.
Efinix's Titanium Ti375 FPGA is a high-density device designed for applications demanding low power consumption alongside robust processing capabilities. This FPGA is embedded with the Quantum® compute fabric, an architecture that delivers significant power, performance, and area benefits. Notably, the Ti375 incorporates a hardened quad-core RISC-V block, various high-speed transceivers for protocols like PCIe Gen4, and supports LPDDR4 DRAM for efficient memory operations. The Ti375 excels in its ability to facilitate high-speed communications and sophisticated data processing, owing in part to its multiple full-duplex transceivers. These transceivers support a swath of industries by enabling data rates up to 16 Gbps for PCIe interfaces or up to 10 Gbps for Ethernet links. Additionally, the FPGA is equipped with advanced MIPI D-PHY functionalities, crucial for applications in the fields of imaging and vision. This versatile FPGA supports the development of complex systems, from industrial automation to advanced consumer electronics, by offering features like extensive I/O configurations and on-board debugging capabilities. With the comprehensive Efinity software suite, developers can streamline the transition from RTL design to bitstream generation, enhancing project timelines significantly. Whether used as a standalone solution or integrated into a larger system, the Ti375 provides an adaptable framework for modern design challenges.
The Chipchain C100 is a sophisticated single-chip solution tailored for Internet of Things (IoT) applications. It incorporates a 32-bit RISC-V CPU, capable of running at speeds up to 1.5GHz, making it ideal for high-performance computing tasks. With built-in RAM and ROM, it provides efficient processing and memory capabilities. The C100 features integrated wireless communication through Wi-Fi, alongside various transmission interfaces. This makes the chip versatile for a wide range of applications while maintaining low power consumption. It also includes essential components like an analog-to-digital converter (ADC), low dropout regulators (LDO), and a temperature sensor. Designed for ease of use in diverse IoT environments, the C100 facilitates simpler, faster development, making it suitable for security systems, smart homes, toys, games, and healthcare applications. Its integration of multiple functionalities in a compact design ensures reliable performance across industries.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The MIPI D-PHY Analog Transceiver is a crucial component for applications requiring efficient data communication between processors and displays or cameras. This transceiver IP core supports multiple MIPI standards, integrating easily with MIPI CSI-2 and DSI specifications to deliver superior data transmission capabilities. This IP is characterized by its robust analog front-end, which handles electrical signal generation and reception, providing seamless control over I/O activities. The D-PHY transceiver boasts low power operation, essential for consumer electronics such as smartphones and tablets that demand both high performance and energy efficiency. Widely utilized in the industry, the IP supports configurations as a transmitter, receiver, or transceiver, ensuring flexible adoption for varied applications. Its adaptability across different product designs allows it to quickly integrate into systems, propelling fast development cycles and enhancing market competitiveness.
KNiulink offers a versatile SerDes solution designed for high-speed data transmission with applications across PCIe, Rapid IO, and SATA/SAS protocols. This solution is engineered with advanced architectures and technologies to meet the demands of low power consumption while maintaining high performance. It features configuration flexibility, enabling seamless integration with user logic or SOC for optimized system performance.
Tentiva is a versatile Video FMC board designed for modular video processing applications. It stands out with its high degree of customization enabled by two dedicated PHY slots, which support an array of PHY cards for flexible connectivity. The PHY slots facilitate robust high-speed communication, with data rates reaching up to 20 Gbps, ideal for demanding video processing tasks. Modularity is at the heart of the Tentiva design, allowing users to effortlessly add or remove PHY cards as needed. This adaptability makes it suitable for a wide range of applications, whether it's for cascading multiple boards or supporting different video standards. The available PHY cards include DisplayPort transmitters and receivers as well as embedded DisplayPort solutions, covering a broad spectrum of connectivity needs. Integrated to work with FPGA development boards equipped with FMC headers, Tentiva ensures compatibility across a variety of vendor products, offering seamless integration for video processing workflows. Its design is particularly beneficial for developers seeking a scalable and adaptable solution to integrate into FPGA-based systems.
The X1 is an advanced SATA SSD controller crafted for high-performance and demanding industrial applications. It integrates a 32-bit dual-core microprocessor optimized for flash memory management, utilizing specialized instruction sets and hardware accelerators. The controller also features hyMap, a customizable sub-page-based Flash Translation Layer, and FlashXE eXtended Endurance technology, which enhances durability and reliability. Designed to offer superior power efficiency, the X1 also includes hyReliability flash management system for comprehensive wear leveling, read disturb management, dynamic data refresh, and power fail management, thus ensuring optimal reliability and endurance in industrial settings.
The ADNESC ARINC 664 End System Controller is crafted to meet the challenges of modern aerospace applications, where high-speed data handling and compliance with stringent industry standards are paramount. This controller supports a target device-independent approach, leveraging generic VHDL code to ensure adaptability across various hardware platforms. With the capability to manage multiple host interfaces at data rates up to 400 Mbit/s, it sustains high-performance requirements needed in sophisticated avionics setups. The inclusion of embedded SRAM enhances the controler's efficiency, facilitating swift data processing and storage. Such features enable robust communication systems that are essential for cutting-edge aeronautic applications, supporting seamless integration into a mixed-fleet environment. Developed with a design process that aligns with RTCA DO-254 DAL A, the ADNESC ARINC 664 Controller ensures adherence to industry’s highest reliability and safety criteria. It's a testament to IOxOS Technologies' commitment to delivering solutions that address the complexities and strict safety standards of aerospace systems.
The MIPI Video Processing Pipeline leverages the MIPI standards to enable efficient video data processing tailored for embedded FPGA platforms. This comprehensive solution supports key video protocols like Avalon and AXI-4 Streaming, adapting easily to various sensor video formats and frame rates. The pipeline handles resolutions reaching 4K at 60 frames per second, catering to high-definition video requirements in consumer electronics and professional imaging markets. With its scalable architecture, it allows multiple pixels per clock processing without compromising on performance, aiding in resource optimization. StreamDSP's pipeline supports customizable stages such as defective pixel correction, color correction, and chroma resampling, each pivotal in achieving high-quality video output. This flexibility ensures the IP can be utilized in diverse applications ranging from automotive infotainment systems to industrial imaging setups.
Designed for the aerospace sector, the ARINC664 Switch core encapsulates the switching capabilities required within an ARINC664 network. This core incorporates ARINC664 part 7 specifications, enabling it to function robustly as a networking switch aimed at maintaining seamless communication over extended avionics systems.\n\nThe core facilitates smooth packet routing across different network layers, ensuring each data packet reaches its intended recipient with the lowest possible latency. Its architecture supports multiple parallel data streams and prioritizes traffic according to predefined rules, crucial for environments where real-time data transmission is critical.\n\nBuilt for flexibility and reliability, the ARINC664 Switch core can adapt to various aircraft communication needs, interfacing effectively with other network elements such as end systems and routers. It allows for scalable implementations, supporting a growing network infrastructure in contemporary and future aeronautics technology landscapes.
XtremeSilica’s MIPI solutions cater to the high-performance requirements of mobile and automotive applications. Offering seamless integration, these solutions provide essential high-speed connectivity for multimedia and sensor interfaces crucial for advanced user experiences. The MIPI IP addresses the need for reduced power consumption while achieving high data transfer rates, a fundamental requirement in compact, portable devices. This balance ensures optimal performance without compromising on device efficiency or battery life. Its robust interoperability with various tools and platforms facilitates the development of innovative mobile solutions and next-gen automotive systems. MIPI’s scalable framework supports extensive customization, making it suitable for a variety of applications requiring reliable, high-speed interaction.