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The 2nd Generation Akida builds upon BrainChip's neuromorphic legacy, broadening the range of supported complex network models with enhancements in weight and activation precision up to 8 bits. This generation introduces additional energy efficiency, performance optimizations, and greater accuracy, catering to a broader set of intelligent applications. Notably, it supports advanced features like Temporal Event-Based Neural Networks (TENNs), Vision Transformers, and extensive use of skip connections, which elevate its capabilities within spatio-temporal and vision-based applications. Designed for a variety of industrial, automotive, healthcare, and smart city applications, the 2nd Generation Akida boasts on-chip learning which maintains data privacy by eliminating the need to send sensitive information to the cloud. This reduces latency and secures data, crucial for future autonomous and IoT applications. With its multipass processing capabilities, Akida addresses the challenge of limited hardware resources smartly, processing complex models efficiently on the edge. Offering a flexible and scalable IP platform, it is poised to enhance end-user experiences across various industries by enabling efficient real-time AI processing on compact devices. The introduction of long-range skip connections further supports intricate neural networks like ResNet and DenseNet, showcasing Akida's potential to drive deeper model efficiencies without excessive host CPU calculation dependence.
Overview: CMOS Image Sensors (CIS) often suffer from base noise, such as Additive White Gaussian Noise (AWGN), which deteriorates image quality in low-light environments. Traditional noise reduction methods include mask filters for still images and temporal noise data accumulation for video streams. However, these methods can lead to ghosting artifacts in sequential images due to inconsistent signal processing. To address this, this IP offers advanced noise reduction techniques and features a specific Anti-ghost Block to minimize ghosting effects. Specifications: Maximum Resolution o Image : 13MP o Video : 13MP@30fps -Input formats : YUV422–8 bits -Output formats o DVP : YUV422-8 bits o AXI : YUV420, YUV422 -8 bits-Interface o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) Features: Base Noise Correction: AWGN reduction for improved image quality Mask Filter: Convolution-based noise reduction for still images Temporal Noise Data Accumulation: Gaussian Distribution-based noise reduction for video streams using 2 frames of images 3D Noise Reduction (3DNR): Sequential image noise reduction with Anti-ghost Block Motion Estimation and Adaptive: Suppresses ghosting artifacts during noise reduction Real-Time Processing: Supports Digital Video Port (DVP) and AXI interfaces for seamless integration Anti-Ghost Real time De-noising output
0.75V ESD power protection. The ESD clamp is designed to provide protection for 0.75 V Analog and Core domain using 0.75V FinFet transistors in TSMC N3E process. The target ESD robustness can be selected.
The LVDS IP is designed to provide Low Voltage Differential Signaling interfaces, a method known for reducing electromagnetic interference while enabling high-speed data transfer across circuits. Suitable for applications in displays and telecommunications, this IP supports robust signal integrity, adhering to strict technical and operational standards. Engineered for versatility, the LVDS IP operates efficiently over long distances, making it ideal for complex electronic environments where signal fidelity is paramount. Its adaptability allows for seamless integration into various system architectures. This IP focuses on minimizing power consumption without sacrificing performance, addressing the energy efficiency needs of modern electronic systems. Its compatibility and advanced design ensure that it meets diverse application requirements where high-speed, low-noise data communication is critical.
MetaTF is BrainChip's toolset designed to facilitate the development and deployment of neural networks on their Akida platform. It simplifies the process of leveraging BrainChip’s AI capabilities by allowing the conversion of existing TensorFlow models to the Akida platform. Using Python and associated tools like Jupyter notebooks, MetaTF offers a seamless environment for training and deploying AI models optimized for event-based computations. The framework consists of multiple Python packages: the Akida package which provides an interface to BrainChip's neuromorphic chip, and CNN2SNN to convert convolutional neural networks for event domain processing. MetaTF's core value lies in streamlining the creation of low-latency, low-power networks that are inherently suited for BrainChip's portfolio of AI processors. With a built-in model zoo and performance simulation features, MetaTF enables users to evaluate and optimize models efficiently. This toolset ensures smooth integration with existing AI workflows by removing the necessity to adopt new machine learning paradigms completely, making it a vital component in BrainChip’s AI enablement strategy.
The Rambus DDR5 Server DIMM Chipset is designed to deliver market-leading performance in data center servers. This chipset supports both RDIMM and MRDIMM configurations, featuring DDR5 Registering Clock Drivers (RCD), Power Management ICs (PMICs), and Serial Presence Detect Hubs (SPD Hub). It also includes Temperature Sensors (TS) for enhanced thermal management. The MRDIMM variant additionally offers Multiplexed Registering Clock Drivers (MRCD) and Multiplexed Data Buffers (MDB). Performance is maximized at speeds up to 12800 MT/s, preparing servers for the demands of upcoming data-intensive applications.
Overview: Lens distortion is a common issue in cameras, especially with wide-angle or fisheye lenses, causing straight lines to appear curved. Radial distortion, where the image is expanded or reduced radially from the center, is the most prominent type. Failure to correct distortion can lead to issues in digital image analysis. The solution involves mathematically modeling and correcting distortion by estimating parameters that determine the degree of distortion and applying inverse transformations. Automotive systems often require additional image processing features, such as de-warping, for front/rear view cameras. The Lens Distortion Correction H/W IP comprises 3 blocks for coordinate generation, data caching, and interpolation, providing de-warping capabilities for accurate image correction. Specifications: Maximum Resolution: o Image: 8MP (3840x2160) o Video: 8MP @ 60fps Input Formats: YUV422 - 8 bits Output Formats: o AXI: YUV420, YUV422, RGB888 - 8 bits Interface: o ARM® AMBA APB BUS interface for system control o ARM® AMBA AXI interface for data Features: Programmable Window Size and Position Barrel Distortion Correction Support Wide Angle Correction up to 192° De-warping Modes: o Zoom o Tilt o Pan o Rotate o Side-view Programmable Parameters: o Zoom Factor: controls Distance from the Image Plane to the Camera (Sensor)
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARM® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications: Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps Input Formats: Bayer-8, 10, 12, 14 bits Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features: Defective Pixel Correction: On-The-Fly Defective Pixel Correction 14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5% 2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm Color Correction Matrix: 3x3 Matrix Bayer Gamma Correction: 19 points RGB Gamma Correction: 19 points Color Enhancement: Hue/Sat/∆-L Control for R/G/B/C/M/Y Channels High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting Auto White Balance: Based on R/G/B Feed-Forward Method Auto Focus: 2-Type 6-Region AF Value Return
Overview: The DDR5 RCD Controller is a registering clock driver utilized in DDR5 RDIMMs and LRDIMMs. It buffers the Command/Address (CA) bus, chip selects, and clock signals between the host controller and DRAMs. Additionally, it establishes a BCOM bus to control data buffers in LRDIMMs. Key Features: Compliance with JEDEC's JESD82-511 Maximum SCL Operating speed of 12.5MHz in I3C mode DDR5 server speeds up to 4800MT/s Dual-channel configuration with 32-bit data width per channel Support for power-saving mechanisms Rank 0 & rank 1 DIMM configurations Loopback and pass-through modes BCOM sideband bus for LRDIMM data buffer control In-band Interrupt support Packet Error Check (PEC) CCC Packet Error Handling Error log register Parity Error Handling Interrupt Arbitration I2C Fast-mode Plus (FM+) and I3C Basic compatibility Switch between I2C mode and I3C Basic Clearing of Status Registers Compliance with JESD82-511 specification I3C Basic Common Command Codes (CCC) Applications: RDIMM LRDIMM AI (Artificial Intelligence) HPC (High-Performance Computing) Data-intensive applications
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features: Supports UCIe 1.0 Specification Supports CXL 2.0 and CXL 3.0 Specifications Supports PCIe Gen6 Specification Supports PCIe Gen5 and older versions of PCIe specifications Supports single and two-stack modules Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers Supports CXL 3.0 256Byte flit mode Supports PCIe Gen6 flit mode Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules Supports sideband and Mainband signals Supports Lane repair handling Data to clock point training and eye width sweep support from transmitter and receiver ends UCIe controller can work as Downstream or Upstream Main Band Lane reversal supported Dynamic sense of normal and redundant clock and data lines activation UCIe enumeration through DVSEC Error logging and reporting supported Error injection supported through Register programming RDI/FDI PM entry, Exit, Abort flows supported Dynamic clock gang at adapter supported Configurable Options: Maximum link width (x1, x2, x4, x8, x16) MPS (128B to 4KB) MRRS (128B to 4KB) Transmit retry/Receive buffer size Number of Virtual Channels L1 PM substate support Optional Capability Features can be Configured Number of PF/VFDMA configurable Options AXI MAX payload size Variations Multiple CPI Interfaces (Configurable) Cache/memory configurable Type 0/1/2 device configurable
Overview: RCCC and RCCB in ISP refer to Red and Blue Color Correction Coefficients, respectively. These coefficients are utilized in Image Signal Processing to enhance red and blue color components for accurate color reproduction and balance. They are essential for color correction and calibration to ensure optimal image quality and color accuracy in photography, video recording, and visual displays. The IP is designed to process RCCC pattern data from sensors, where green and blue pixels are substituted by Clear pixel, resulting in Red or Clear (Monochrome) format after demosaicing. It supports real-time processing with Digital Video Port (DVP) format similar to CIS output. RCCB sensors use Clear pixels instead of Green pixels, enhancing sensitivity and image quality in low-light conditions compared to traditional RGB Bayer sensors. LOTUS converts input from RCCB sensors to a pattern resembling RGB Bayer sensors, providing DVP format interface for real-time processing. Features: Maximum Resolution: 8MP (3840h x 2160v) Maximum Input Frame Rate: 30fps Low Power Consumption RCCC/RCCB Pattern demosaicing
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller, the agilePMU Subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features: Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0 Support for Single master and multiple slaves per interface port Single Data Rate (SDR) and Double Data Rate (DDR) support Source synchronous clocking Deep Power Down (DPD) enter and exit commands Eight IO ports in standard, expandable based on system requirements Optional Data Strobe (DS) for write masking bit wide SDR transfer support Profile 1.0 Commands for non-volatile memory device management Profile 2.0 Commands for read or write data for various slave devices Applications: Consumer Electronics Defense & Aerospace Virtual Reality Augmented Reality Medical Biometrics Automotive Devices Sensor Devices
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), from master host bus. This SPD5 has Two wire serial interface like SCL, SDA
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
Overview: Human eyes have a wider dynamic range than CMOS image sensors (CIS), leading to differences in how objects are perceived in images or videos. To address this, CIS and IP algorithms have been developed to express a higher range of brightness. High Dynamic Range (HDR) based on Single Exposure has limitations in recreating the Saturation Region, prompting the development of Wide Dynamic Range (WDR) using Multi Exposure images. The IP supports PWL companding mode or Linear mode to perform WDR. It analyzes the full-image histogram for global tone mapping and maximizes visible contrast in local areas for enhanced dynamic range. Specifications: Maximum Resolution: o Image: 13MP o Video: 13MP @ 60fps (Input/Output) Input Formats (Bayer): o HDR Linear Mode: Max raw 28 bits o Companding Mode: Max PWL compressed raw 24 bits Output Formats (Bayer): 14 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Video data stream interface Features: Global Tone Mapping based on histogram analysis o Adaptive global tone mapping per Input Images Local Tone Mapping for adaptive contrast enhancement Real-Time WDR Output Low Power Consumption and Small Gate Count 28-bit Sensor Data Interface
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
The ADQ35 offers a dual-channel, 12-bit configuration with a sampling rate of up to 10 GSPS. This digitizer is designed for high-performance applications, featuring up to 2.5 GHz input bandwidth and a programmable DC-offset. With 8 Gbyte onboard memory and an open FPGA, it allows custom real-time digital signal processing. It supports peer-to-peer streaming at rates up to 14 Gbyte/s, making it ideal for scientific and industrial applications.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features: CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X PCIe Compatibility: Supports PCIe spec 6.0/5.0 CPI Interface: Support for CPI Interface AXI Interface: Configurable AXI master, AXI slave Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16 Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode Register Checks: Configuration and Memory Mapped registers Dual Mode: Supports Dual Mode operation Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers CXL Support: Can function as both CXL host and device Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized) Power Management: Supports Power Management features Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD Testing: Compliance Testing and Error Scenarios support
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The NMP-750 is a high-performance accelerator designed for edge computing, particularly suited for automotive, AR/VR, and telecommunications sectors. It boasts an impressive capacity of up to 16 TOPS and 16 MB local memory, powered by a RISC-V or Arm Cortex-R/A 32-bit CPU. The three AXI4 interfaces ensure seamless data transfer and processing. This advanced accelerator supports multifaceted applications such as mobility control, building automation, and multi-camera processing. It's designed to cope with the rigorous demands of modern digital and autonomous systems, offering substantial processing power and efficiency for intensive computational tasks. The NMP-750's ability to integrate into smart systems and manage spectral efficiency makes it crucial for communications and smart infrastructure management. It helps streamline operations, maintain effective energy management, and facilitate sophisticated AI-driven automation, ensuring that even the most complex data flows are handled efficiently.
The Tianqiao-70 CPU core by StarFive is a low-power RISC-V processor, designed specifically to address the needs of commercial applications that prioritize energy efficiency. This 64-bit CPU core is versatile, catering to various sectors including mobile devices, IoT applications, and intelligent consumer electronics that demand performance without compromising on power. Designed with efficient power utilization at its core, the Tianqiao-70 is tailored to offer high computation capacity while keeping energy consumption minimal, thereby extending device battery life and reducing operational costs. This processor core supports a vast spectrum of computational tasks while maintaining low-level power metrics, an essential factor in mobile and embedded applications. Through its effective design, the Tianqiao-70 continues to support a wide array of tasks efficiently, allowing businesses to lower their energy usage while achieving powerful processing capabilities. This core stands as an ideal solution for forward-thinking organizations that value sustainability and legacy support in their tech stack.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications: Supports PCIe Gen 6 and Pipe 5.X Specifications Core supports Flit and non-Flit Mode Lane Configurations: X16, X8, X4, X2, X1 AXI MM and Streaming supported Supports Gen1 to Gen6 modes Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s PAM support when operating at 64GT/s Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b Supports SerDes and non-SerDes architecture Optional DMA support as plugin module Support for alternate negotiation protocol Can operate as an endpoint or root complex Lane polarity control through register Lane de-skew supported Support for L1 states and L0P Support for SKP OS add/removal and SRIS mode No equalization support through configuration Deemphasis negotiation support at 5GT/s Supports EI inferences in all modes Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Analog Circuit Works specializes in designing digital to analog converters (DACs) focused on power efficiency and performance. These DACs are engineered to align with specific bandwidth requirements, ensuring efficient driving of loads under varying operational conditions while maintaining desired accuracy across multiple applications. Their DAC portfolio includes solutions optimized for a range of resolutions and sample rates, demonstrating flexibility in design to accommodate different system requirements. By focusing on power efficiency, they have developed DACs that support enhanced operational lifespans and energy conservation, making them ideal for energy-sensitive applications. The ability to deliver application-specific DAC solutions that can seamlessly integrate into complex systems underscores their commitment to quality and precision. These converters play a crucial role in translating digital signals back to analog form, enabling high-fidelity signal processing and performance in demanding electronic environments.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Panmnesia's CXL 3.1 Switch is a pivotal component in networking a vast array of CXL-enabled devices, setting the bar with its exceptional scalability and diverse connectivity. The switch supports seamless integration of hundreds of devices including memory, CPUs, and accelerators, facilitating flexible, high-performance configurations suited to demanding applications in data centers and beyond. Panmnesia's design enables easy scalability and efficient memory node expansion, reflecting their dedication to resource-efficient memory management. The CXL 3.1 Switch features a robust architecture that supports a wide array of network topologies, allowing for multi-level switching and complex node configurations. Its design addresses the unique challenges of composable server architecture, enabling fine-grained resource allocation. The switch leverages Panmnesia's proprietary CXL technology, underpinning its ability to perform management tasks across integrated memory spaces with minimal overhead, crucial for achieving high-speed, low-latency data exchange. Incorporating CXL standards, it is fully compatible with both legacy and next-generation devices, ensuring broad interoperability. The architecture allows servers to tailor resource availability by employing type-specific CXL features, such as port-based routing and multi-level switching. These features empower operators with the tools to configure extensive networks of diverse devices efficiently, thereby maximizing data center performance while minimizing costs.
The Coherent Network-on-Chip (Coherent NOC) by SkyeChip is a high-performance interconnect solution aimed at memory-coherent systems. It is designed to diminish routing inefficiencies in many-core environments, thus supporting high operating frequencies up to 2 GHz. Integration with proprietary coherency handlers and compatibility with SkyeChip's Non-Coherent NOC enables flexible system designs capable of managing complex tasks in advanced computing applications.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
The KL730 AI SoC is powered by Kneron's innovative third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This architecture offers enhanced efficiency for the latest CNNnetwork architectures and serves transformer applications by reducing DDR bandwidth requirements significantly. The chip excels in video processing, supporting 4K 60FPS output and excelling in areas such as noise reduction and low-light imaging. It's ideal for applications in intelligent security, autonomous driving, and video conferencing, among others.
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its goal is to promote design reuse by addressing system-on-chip integration issues. This is accomplished by providing a standard interface for IP cores. This increases the system's mobility and stability, resulting in a shorter time-to-market for end users.
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that can stream high-speed data, read and write registers and memory, and operate off-chip devices. Platform Designer components incorporate these standard interfaces. Furthermore, you can include Avalon APIs in custom components, increasing the interoperability of designs.
KPIT's AUTOSAR and Adaptive AUTOSAR Solutions provide robust frameworks for automotive software development. Catering to the evolving needs of smart vehicles, these solutions ensure high reliability, safety, and compliance with industry standards. KPIT's middleware development enhances the adaptability and integration of various software modules, supporting clients in managing the complexities of modern vehicle platforms and accelerating the release of innovative automotive technologies.
Silvaco's Automotive IP is engineered for in-vehicle networks and covers an extensive range of controllers adhering to automotive standards like FlexCAN with CAN-FD, FlexRay, and LIN. These products are production-proven and designed to integrate seamlessly into the SoC's subsystems, ensuring reliability and a high degree of interoperability. This suite of automotive IP is packaged to simplify design processes, reduce time-to-market, and ensure compliance with industry safety standards, making it indispensable in the evolving automotive landscape.
Overview: RGB-IR features in ISP enable the capture and processing of Red, Green, Blue, and Infrared (IR) light data in an Image Signal Processing (ISP) system. This functionality enhances image quality by extracting additional information not visible to the human eye in standard RGB images. By integrating IR and RGB data into the demosaic processing pipeline, the ISP can enhance scene analysis, object detection, and image clarity in applications such as surveillance, automotive, and security systems. Features: IR Core - 4Kx1EA: 4K Maximum Resolution: 3840h x 2160v @ 30fps IR Color Correction 3.99x support IR data Full-size output / 1/4x subsample support (Pure IR Pixel data) Only RGB-IR 4x4 pattern support IR data Crop support
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
Exostiv offers comprehensive functionality for in-depth monitoring and capturing of internal FPGA signals at operational speeds. It enables engineers to conduct precise and cost-effective analysis of their FPGA designs in realistic environments, overcoming the limitations of traditional simulation approaches. By providing extensive data capture abilities, Exostiv is an essential tool for minimizing engineering costs and ensuring the highest levels of design integrity. At the core of Exostiv is its versatility in compatibility, supporting a wide range of FPGA devices and ensuring adaptability to various prototyping boards. Its integration is bolstered by a range of connector options—including QSFP28 and Samtec ARF-6—providing small-footprint solutions ideal for space-tight configurations. With impressive data rates and bandwidth options, Exostiv propels performance analysis to new heights by allowing accurate trace capture and design visualization at speed. Engineers benefit from Exostiv’s ability to perform real-time signal monitoring directly on FPGA prototypes. This leads to substantial reductions in potential bugs reaching production, as the tool highlights discrepancies that might not be visible during simulations. Whether used for debugging or for SoC pre-production testing, Exostiv plays a vital role in streamlining engineering workflows, offering a blend of ease-of-use and powerful capabilities to address the most demanding validation scenarios.
The Origin E1 is an optimized neural processing unit (NPU) targeting always-on applications in devices like home appliances, smartphones, and security cameras. It provides a compact, energy-efficient solution with performance tailored to 1 TOPS, making it ideal for systems needing low-power and minimal area. The architecture is built on Expedera's unique packet-based approach, which enables enhanced resource utilization and deterministic performance, significantly boosting efficiency while avoiding the pitfalls of traditional layer-based architectures. The architecture is fine-tuned to support standard and custom neural networks without requiring external memory, preserving privacy and ensuring fast processing. Its ability to process data in parallel across multiple layers results in predictive performance with low power and latency. Always-sensing cameras leveraging the Origin E1 can continuously analyze visual data, facilitating smoother and more intuitive user interactions. Successful field deployment in over 10 million devices highlights the Origin E1's reliability and effectiveness. Its flexible design allows for adjustments to meet the specific PPA requirements of diverse applications. Offered as Soft IP (RTL) or GDS, this engine is a blend of efficiency and capability, capitalizing on the full scope of Expedera's software tools and custom support features.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
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