All IPs > Multimedia > H.264
In today's digital age, the demand for high-quality video streaming and broadcasting is ever-growing. H.264 semiconductor IPs provide a robust foundation for efficiently compressing and decompressing video data, enabling seamless and high-performance multimedia applications. As a widely-adopted video coding standard, H.264 is integral in the delivery of clear, crisp images while minimizing bandwidth usage and storage requirements.
The H.264 standard is known for its high compression efficiency, allowing developers to create video solutions that deliver superior image quality without significant resource expenditure. This is particularly crucial for applications such as video conferencing, digital TV broadcasting, and online video streaming services. H.264 semiconductor IPs are designed to be flexible and reliable, supporting a broad range of devices from mobile gadgets to high-end broadcasting systems.
Products in the H.264 semiconductor IP category include a variety of encoders and decoders, optimized for different performance levels and integration requirements. These IPs are essential components for companies looking to enhance their multimedia offerings while ensuring interoperability with existing systems. Whether you are developing software for video editing applications or hardware for digital media broadcasting, H.264 IPs offer scalable solutions that meet diverse technical demands.
With advancements in video technology, the importance of efficient semiconductor IPs like H.264 continues to rise. By integrating these IPs into your products, you can tap into the potential of high-definition video experiences, ensuring that your users enjoy smooth, buffer-free streaming and playback. Explore our range of H.264 semiconductor IPs to find the right fit for your multimedia projects, enabling your technology to reach its full potential in today's competitive digital landscape.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores from A2e Technologies are industry-leading solutions optimized for high-speed video encoding with minimal latency. Specially tailored for FPGA applications, this core ensures compliance with the H.264 Baseline and offers configurations to suit varying performance needs, such as low-cost evaluation licenses for flexibility. These cores are noted for their exceptionally compact size and rapid processing capabilities, enabling them to achieve 1080p at 60 frames per second with remarkable efficiency. One of the project's standout features is the 1ms latency at 1080p30, which is among the fastest in the industry. This core also supports custom configurations, allowing adjustments to pixel depth, resolution, and more, making it a versatile choice for developers looking to integrate video encoding in their systems. Moreover, these cores are ITAR compliant, offering a secure and adaptable solution for high-performance FPGA design. The scalability and customization options, including support for various pixel depths and resolutions, make these H.264 cores suitable for a wide array of applications, from real-time video streaming to embedded systems in industrial automation. By leveraging this advanced technology, A2e Technologies provides a robust solution that meets stringent industry standards and addresses specific customer needs effectively.
The MIPI DSI-2 Transmitter IP from Arasan is engineered for streamlined communication between processors and display panels, a critical component in the rapidly evolving displays of mobile devices. Aligning with the MIPI DSI standards, this Transmitter IP ensures interoperability and high-speed data transmission, achieving the requisite performance for vivid and responsive displays. Key attributes include multi-lane data handling, reduced data transmission latency, and comprehensive support for various display configurations and modes. Arasan's DSI-2 Transmitter is optimized for power efficiency, employing techniques like low-power modes and clock gating to curtail power consumption and extend device battery life. Customers benefit from Arasan's extensive experience and support throughout the integration process, ensuring a robust, reliable, and compliant display solution that meets the needs of next-generation mobile applications.
Allegro DVT's HEVC/H.265 Encoder is designed to provide high-quality video compression while maintaining low bit rates, making it ideal for both streaming and storage applications. With the ability to handle up to 4K resolution and beyond, this encoder supports the H.265/HEVC standard, which is known for its superior compression efficiency over previous standards like AVC/H.264. This video encoder is particularly suited to applications where bandwidth conservation is critical, such as video streaming over the internet, satellite broadcasting, and IPTV. The encoder implements advanced compression techniques to reduce the file size while preserving the video quality, delivering smooth and uninterrupted video streams even under variable network conditions. Engineered with versatility in mind, this encoder supports a broad range of features such as adaptive coding, error resilience, and low latency processing. This makes it suitable for real-time broadcasting scenarios where time is of the essence. Its configurable architecture allows it to be tailored to meet specific end-user needs, ensuring optimal performance across various environments.
The DSC Encoder by Trilinear Technologies efficiently compresses digital video streams, adhering to the VESA Display Stream Compression 1.2a standards. This encoder is engineered for high-speed, real-time operations, making it suitable for both consumer technology and professional-grade applications. Its primary function is to reduce the bandwidth required for transmitting high-resolution video data, crucial for today's demanding multimedia environments. By implementing state-of-the-art compression techniques, the DSC Encoder allows for the seamless handling of up to 16K visual data without degrading quality, making it invaluable for applications that necessitate high-definition displays. This includes everything from advanced gaming systems and home entertainment setups to professional broadcasting and video production devices. Designed to integrate effortlessly with FPGAs and SoCs, the DSC Encoder facilitates the handling of large amounts of data with minimal power consumption, ensuring efficient processing without overheating or significant energy use. It is an indispensable tool for developers looking to incorporate higher quality media experiences without the technological constraints of older systems.
The JPEG Encoder for Image Compression is designed to deliver efficient lossy compression for various imaging applications. This encoder is compliant with the Baseline JPEG standard (ITU T.81), ensuring a balance between compression efficiency and image quality. It supports pixel depths of up to 12 bits, although 8 bits is the default setting. The encoder provides super low latency, making it ideal for rolling shutter cameras, and is available in multiple configurations to suit different application needs. This encoder is particularly adaptable for multimedia applications requiring high-speed processing, including motion JPEG, thanks to its dual-pipe design that allows simultaneous encoding for formats like YUV422. This setup supports resolutions such as 1280x720 at 60 fps with a pixel clock of 100 MHz, although platform-specific optimizations can increase speed. The encoder operates without external RAM, relying only on FPGA and Ethernet PHY, which not only reduces power consumption but also simplifies hardware requirements. Additionally, the JPEG Encoder is verified extensively against standard compliance through detailed simulation models that ensure both bit and cycle accuracy. The encoder can be implemented in various SoCs and integrates smoothly with existing systems, thanks to its adaptable architecture that supports various network streaming standards and embedded applications.
The DSC Decoder is a cutting-edge solution geared towards decoding Display Stream Compression (DSC) data, ensuring optimal performance in delivering high-definition video content. Aligned with the VESA DSC 1.2a standard, this decoder allows for real-time decompression of video streams with high efficiency, ideal for devices and systems needing to manage bandwidth while maintaining a superior visual quality output. Its application stretches across industries, catering to devices that require high-performance video processing like professional display systems, gaming consoles, and even military-grade visual equipment. The decoder supports integration with both SoCs and FPGAs, offering flexibility and adaptability without compromising the integrity or speed of the data being processed. The DSC Decoder’s engineering excellence enables it to manage high-resolution videos up to 16K seamlessly, offering an uncompromised experience in graphics rendering and broadcast quality. It plays a vital role in environments where performance, speed, and video quality cannot be sacrificed, making it a key component in the next generation of multimedia solutions.
Ocean Logic has developed an advanced H.264 Baseline Encoder that uses Compressed Frame Store (CFS) technology, offering significant innovations in video encoding. This encoder is particularly noted for its compatibility with existing H.264 decoders and its ability to compress reference frames by a ratio of 8 to 16:1. This compression efficiency effectively reduces the necessity for external DRAM and lessens power demands, a substantial benefit in integrated systems where space and energy are constrained. The proprietary CFS technology is capable of embedding within the chip, enhancing the power and bandwidth advantages of the H.264 encoder. Its high compression capabilities make it particularly suitable for System on Chip (SoC) designs, enabling efficient H.264 encoding of 1080p video at 30 frames per second with both I and P frames, without relying on external memory resources. This self-contained system significantly enhances power efficiency and reliability, making it an optimal solution for devices requiring high-quality video processing without the added burden of separate DRAM chips. Engineers and system designers benefit from the IP's robustness, facilitated by its broad patent protection across key global markets. The IP not only heralds advancements in efficiency but also presents opportunities for integrating superior video encoding capabilities into a variety of applications, from communication devices to distributed video systems.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
Packetcraft's Bluetooth LE Audio Solutions represent a robust package designed to support next-generation wireless audio experiences. These solutions encompass a wide array of capabilities, including full support for both host and controller functions as well as integration with the LC3 codec. This technological framework is built to streamline the transition to Bluetooth LE Audio, supporting innovative features like Auracast broadcast audio and true wireless stereo (TWS) configurations. The LE Audio Solutions provided by Packetcraft assure adaptability with popular chipsets, thus offering a great degree of flexibility to audio product manufacturers. With a commitment to seamless integration, Packetcraft’s offerings are optimized to enhance the efficiency of wireless audio systems, providing superior audio quality and extended battery life. Beyond mere audio transmission, these solutions are primed to fully leverage the advanced functionalities of Bluetooth 5.4. This enables developers to construct more efficient, feature-rich audio products that can satisfy the sophisticated desires of modern consumers.
The QOI Lossless Image Compression Encoder and Decoder from Ocean Logic represents a breakthrough in image compression technology. It boasts a highly efficient implementation of the QOI algorithm, engineered for both high and low-end FPGA devices. This IP core can achieve processing speeds of up to approximately 800 megapixels per second, even in lower-powered configurations like 4K at 30 frames per second. Its design optimizes processing efficiency while maintaining minimal resource usage, making it an excellent choice for applications requiring high-speed image processing with limited power availability. At the heart of the IP is its ability to handle substantial amounts of data swiftly, without significant energy expenditure, which is crucial for embedding in power-sensitive devices. The compression enables versatile application in diverse sectors, from consumer electronics to advanced computing environments where high throughput and rapid data handling are paramount. For developers and engineers, the QOI Lossless Compression IP offers an accessible and reliable means to incorporate state-of-the-art lossless image compression into their products, enhancing their ability to handle image data efficiently while ensuring fidelity and performance remain uncompromised.
The HEVC Decoder from VYUsync Design Solutions is a top-tier video decoder built for high performance. It complies with HEVC/H.265 standards, providing up to Main 12 422 Profile compatibility. The HEVC Decoder is specially designed for deployment on a wide variety of target FPGAs. Its capability to handle complex video data efficiently makes it ideal for high-definition video streaming applications, ensuring seamless video playback and advanced video processing. This decoder is flexible, scalable, and tailored to meet the rigorous demands of modern video applications, whether they're for broadcasting, professional video recording, or any high-demand video processing role. Focused on maintaining superior color fidelity, the HEVC Decoder supports the 4:4:4 color format, accommodating larger bit depths to ensure refined and nuanced color reproduction. This makes it exceptionally suited for applications in fields that demand high visual fidelity such as professional film production and medical imaging. The decoder’s design assures low latency, enhancing the responsiveness and effectiveness of visual data transmission, which is particularly critical when real-time processing is necessary. The HEVC Decoder is an invaluable component in mission-critical environments. Its robust performance ensures that it can reliably transport and decode video streams even in high-pressure situations. This decoder is also an asset for companies looking to enhance their current video processing capabilities, offering a highly efficient, field-proven IP that can be integrated seamlessly into existing systems.
XtremeSilica's H.265 Codec IP provides an advanced, efficient solution for high-quality video encoding and decoding. Crafted to meet the stringent requirements of modern multimedia applications, this IP ensures efficient video compression, which is crucial for removing data transmission constraints and enhancing storage capabilities. The H.265 Codec IP offers superior performance by delivering exceptional image quality even at lower bit rates compared to its predecessors. This efficiency in compression not only saves on bandwidth but also ensures smoother playback across various devices and platforms, which is vital for today's diverse digital media landscape. Incorporating the H.265 Codec into your design can significantly enhance application versatility, making it suitable for a range of end uses from consumer electronics to professional broadcasting equipment. Its adaptability to different resolutions and frame rates allows developers to create scalable systems that accommodate both current and future media formats.
The H.265 HEVC Decoder System provides an ultra-low latency and standards-compliant solution for decoding high-efficiency video coding on FPGA. This system is optimized to handle 4K UHD content across various industries ranging from broadcast to medical imaging. Built around Korusys's robust codec architecture, this IP is highly configurable and offers comprehensive support for different bit depths and chroma subsampling options, ensuring flexibility for a wide range of applications. The system's high performance and adaptability help meet the demands of modern video processing needs efficiently.
The J1 core cell is a remarkably small and efficient audio decoder that manages Dolby Digital, AC-3, and MPEG audio decompression. With a design that occupies only 1.0 sqmm of silicon area using 0.18u CMOS technology, it delivers a robust solution for decoding 5.1 channel dolby bitstreams and supports data rates up to 640kb/s. The J1 produces high-quality stereo outputs, both normal and Pro-Logic compatible, from Dolby Digital and MPEG-encoded audio, ideal for set-top boxes and DVD applications.
H.264 Baseline, Main and High Profiles, levels 1 - 4.1 Soft IP RTL (Verilog code) Integration Guide
StreamDSP's complete MIPI video processing pipeline offers a comprehensive solution to simplify video integration into embedded FPGA systems. This pipeline supports both Avalon and AXI-4 streaming protocols, accommodating a vast array of sensor video formats and customizable frame rates, including 4K at 60 frames per second and beyond. The flexible architecture facilitates low-latency video processing with the capacity to handle multiple pixels per clock cycle. This enables users to make resource and clock rate trade-off decisions more effectively. The pipeline components can be seamlessly integrated into various system configurations, providing full IP integration and customization services to ensure that each design is optimized for its specific application. The solution simplifies the process of embedding complex video capabilities into FPGAs, making it well-suited for high-performance video applications across different sectors.
The AVC Decoder from VYUsync is engineered to provide top-level decoding performance in compliance with AVC (H.264) standards. Supporting up to 4:2:2 color formats and 10-bit pixel depth, this decoder is tailored for full HD video processing environments. It supports resolutions up to 1920x1080p60, making it highly efficient for applications demanding high-quality video rendition. The development of this decoder places a strong emphasis on flexibility and scalability. It is constructed to work seamlessly with a wide array of performance points and is adaptable to numerous video applications. Whether used in broadcasting workflows or in professional video gear, its design ensures efficient handling of high-resolution video data, affording users superior clarity and color precision. Beyond these applications, the AVC Decoder is particularly valuable in environments that require critical video transport solutions, such as remote surveillance systems. Its low-latency capabilities ensure swift transmission and processing of video streams, which is vital for maintaining situational awareness in aerospace, defense, and live streaming contexts.
The AVC/H.264 Decoder from Allegro DVT is engineered for high-efficiency decoding of the H.264 format, a widely used standard for video compression. This decoder is optimized to support a wide range of applications like digital broadcasting, high-definition television (HDTV), and video conferencing, catering to both emerging and legacy video decoding needs. Designed with a focus on high performance, the IP ensures smooth playback of H.264 encoded streams while minimizing the power consumption, which is critical for battery-operated devices. Key technical capabilities of this decoder include support for multiple video resolutions, scalability in decoding efficiency, and compatibility with varying network conditions. It can handle full HD decoding while maintaining minimal lag and energy usage. The decoder is also adaptable, enabling it to be fine-tuned for specific application requirements, thus providing flexibility in deployment scenarios. The technologies integrated into this IP help streamline the decoding process, ensuring that the video content remains consistent and reliable, regardless of the source or the network environment. This makes the H.264 Decoder from Allegro DVT a preferred choice for high-quality multimedia applications.
The Advanced Video Transmission Toolkit (FV-VTT) from FastVDO is a cutting-edge solution designed to simulate video encoding, forward error correction (FEC), transmission channels, and video quality assessment. This toolkit supports popular video standards like H.264, H.265, H.266, and AV1, along with advanced FECs such as Polar, LDPC, and Turbo codes used in Wifi and 5G standards. Incorporating diverse channel models like AWGN, Rayleigh fading, and burst error channels, FV-VTT is a comprehensive package for video transmission analysis. By accurately simulating varying conditions and assessing received video quality, this toolkit aids in the development of robust video transmission systems capable of maintaining fidelity across different environments. FastVDO's toolkit is instrumental for developers and researchers focused on optimizing video communication technologies, offering insights to improve video delivery and quality in real-world applications. This innovative product embodies FastVDO's commitment to advancing multimedia communication standards, providing powerful tools for video engineers.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The H.264 Encoder by VISENGI is a cutting-edge solution designed to deliver top-notch video compression. It boasts the highest pixel throughput in the industry, enabling UltraHD 4K 60 capabilities on low-range FPGAs and even 8K 30 on mid-range FPGAs like Arria 10 and Zynq. This encoder uses a unique single-engine design to maintain minimal latency, outperforming multi-engine alternatives. There are two variants available: H264E-I, a compact version for applications requiring minimal external memory and lighter compression, and H264E-P, which provides superior compression for more substantial needs. Both versions ensure a processing speed of over 5.2 pixels encoded per cycle, demonstrating high efficiency and throughput across various resolution demands. Another highlight is its versatile resolution support, allowing for continuous adaptation from low to high resolutions—ranging from QVGA to 8K—within the same IP core. This flexibility coupled with comprehensive real-time control options makes it ideal for dynamic and demanding scenarios. Designed for straightforward integration, the encoder uses AXI interfaces and supports a wide range of I/O configurations enhancing its adaptability in multiple environments.
A versatile decoder, the logiJPGD facilitates simultaneous decoding of up to four HD video channels adhering to the JPEG standard Baseline DCT. It is ideal for applications in video over IP, ensuring precise decompression across AMD's All Programmable SoC and FPGA platforms.<br><br>Its ability to manage multiple video streams efficiently makes it a preferred choice in broadcasting, surveillance, and any field requiring robust video data handling. With its emphasis on maintaining video integrity across multiple channels, the logiJPGD supports detailed and accurate video reproduction.<br><br>This IP core positions itself as a cornerstone for multi-stream video processing, offering exceptional decompression capabilities tailored to modern digital video applications. Its integration into existing systems facilitates enhanced functionality without compromising system performance.
MPEG-H Audio System is a cutting-edge audio technology designed for the immersive experiences of modern television and virtual reality platforms. Recognized as a groundbreaking audio system, Fraunhofer IIS developed it to provide an interactive and enveloping audio environment, transforming the way viewers and gamers experience sound in multimedia contexts. Tailored for the demands of both VR and broadcast TV, the system supports a comprehensive 3D sound experience that makes use of state-of-the-art audio encoding. At its core, MPEG-H Audio System allows users to position sound elements freely in a three-dimensional space, enabling an unprecedented level of realism. Whether it's the dramatic soundscapes in film or the all-encompassing audio required for virtual reality games, MPEG-H offers flexibility and precision that cater to a wide audience ranging from everyday users to professional creators. The audio system’s compatibility with the next generation TV standards and its adaptability to various playback environments make it particularly advantageous. Its design seamlessly integrates into existing deployment frameworks, providing dynamic and rich audio experiences without the complexity of previous systems. As such, MPEG-H Audio is poised to redefine the standards of digital audio, making its impact felt across entertainment and content production industries worldwide.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
VISENGI’s H.264 Decoder IP core is designed to complement their H.264 Encoder, ensuring optimal performance and compatibility. It supports multiple profiles including the High 4:4:4 Predictive Profile, which matches the encoding specifications. The decoder achieves a high throughput and maintains low latency, keeping up with the high performance of the encoder. The architecture is scalable, allowing for multiple stream decoding in parallel, which offers flexibility in balancing size, latency, and pixel throughput. The core is not a general-purpose decoder but is crafted to work seamlessly with VISENGI's specific encoder profiles, enhancing performance and reducing latency substantially. With embedded DMA engines for direct memory connections and support for high-latency memories, the interface design is aligned with industry standards, notably the AXI interfaces. The inclusion of motion compensation capabilities further improves efficiency, especially when used in conjunction with VISENGI's advanced encoder variants.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
The logiHDR High Dynamic Range Pipeline is designed to enhance camera image quality by extracting maximum detail from high-contrast scenes, such as objects illuminated by direct sunlight or placed in extreme shadow. Supporting Ultra High Definition (UHD) video, including 4K2Kp60, this pipeline is tailored for applications requiring superior image quality in challenging lighting conditions.<br><br>It excels in scenarios where image detail accuracy is critical, making it ideal for advanced photography, cinematography, and industrial imaging where visual precision significantly impacts outcomes. The logiHDR pipeline is an asset for any high-end video processing application that values detail and dynamic range.<br><br>By facilitating exceptional image capturing capabilities, the logiHDR pipeline enables users to maintain high performance and image quality, even in environments where lighting variations can affect visual clarity. The technology ensures that every scene is captured with the richness and nuance required for professional-grade imaging.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
The JPEG XS technology from intoPIX provides an ideal solution for applications requiring ultra-low latency and superior image quality. Using its refined encoding process, JPEG XS significantly reduces the complexity of video compression, driving efficiency in media workflows. This innovative codec achieves lossy and lossless compression, ensuring that high-quality image delivery is feasible for systems ranging from digital cinema to professional broadcasting. Designed for seamless integration with CPUs, GPUs, FPGAs, and ASICs, JPEG XS is flexible, supporting a wide range of resolutions and color depths. The codec can manage dynamic video feeds from HD up to 16K resolutions, maintaining a smooth viewing experience even under demanding conditions. Its capability to achieve low latency and low power consumption makes it perfect for real-time video applications such as buses, real-time broadcasting, or interactive environments. JPEG XS is uniquely positioned to replace uncompressed workflows, offering compression ratios from 2:1 to 12:1 while maintaining pristine quality. It allows live IP production, remote studios, and various multimedia productions to operate efficiently without compromise. Its robust architecture supports high frame rates and ensures high reliability across various infrastructures. Thus, JPEG XS is not only a codec but a transformational tool for modern video processing challenges.
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
The v-MP6000UDX Visual Processing Unit from videantis is an advanced processor that suits a wide array of AI and embedded applications needing deep learning and computer vision. This universal architecture is designed to handle not just computationally heavy deep learning processes but also video coding, signal, and image processing tasks all within a single unified framework. The platform is tailored for minimizing power consumption while maximizing performance, making it ideal for automotive, gaming, surveillance, and beyond. With versatility at its core, the v-MP6000UDX efficiently runs embedded tasks with seemingly unmatched performance and flexibility. Its architecture allows seamless updates and scaling, which is a game changer for evolving markets that require AI and high-performance computation. It's engineered to support multiple neural network models such as ResNet and MobileNet, alongside customized networks, making integration with the latest AI frameworks like TensorFlow or PyTorch effortless. Moreover, it's crafted with a unique memory architecture to enhance bandwidth while keeping energy use low. This processor's expansive codec library and accelerated video coding support various media standards ideal for modern high-resolution video applications. All these features are manageable through a single software development suite, further simplifying the complexities of advanced AI and high-bandwidth multimedia applications.
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
The logiJPGD-LS represents a high-performance lossless Motion JPEG decoder compliant with Annex H of the ISO/IEC 10918-1 JPEG standard. Engineered to operate on AMD's MPSoC, SoC, and FPGA devices, it effectively handles still image and video decompression with precision and efficiency.<br><br>Perfectly suited for applications where the integrity of video and images must be maintained without loss, such as medical imaging, surveillance, and broadcast. The decoder provides reliable decompression outcomes by ensuring full retention of original image quality.<br><br>Incorporating this IP core into systems reduces the complexity associated with lossless image decompression while optimizing processing speed and resource utilization. The logiJPGD-LS allows for the seamless handling of image data across various demanding applications.
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
The logiJPGE is a versatile Motion JPEG encoder that provides efficient video compression, supporting JPEG standard Baseline DCT. Designed for AMD's All Programmable SoC and FPGA devices, it ensures that high-quality video streams are compressed with precision and efficiency across various applications.<br><br>This encoder is particularly beneficial in environments such as broadcasting and security where rapid, real-time video compression without quality loss is necessary. Its robust design maintains the integrity of video signals during compression, offering a reliable solution for systems demanding consistent video fidelity.<br><br>By delivering flexible and efficient encoding capabilities, the logiJPGE becomes an essential component in managing video streams, facilitating seamless integration into diverse video processing applications. It sets a standard for quality and performance in video compression solutions.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
The SI Neural Network Analog FFT Computer from SiliconIntervention exemplifies a revolutionary approach to frequency domain analysis using analog technology. This device represents a significant leap forward in signal processing by employing a fully analog neural network architecture to realize the Fast Fourier Transform (FFT) task—achieving it faster and more power-efficiently than traditional digital methods. At the core of this innovation is a sophisticated architecture that spans a neural network with fixed coefficients, designed to conduct the FFT through a recursive Radix-2 decimation process. Unlike digital counterparts, the solution unfolds the recursive nature into a fully realized analog computation, which allows for near-instantaneous output with exceptionally low power requirements. The implications of this device extend across various industries, from automotive applications like Lidar to medical devices and voice recognition in AI/IoT spheres. By conducting significant portions of data analysis in the analog domain, the SI Neural Network Analog FFT Computer greatly reduces the data rate and power demand on digital processing resources, thus enhancing overall system efficiency.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The logiJPGE-LS is a robust lossless Motion JPEG encoder conforming to the ISO/IEC 10918-1 JPEG standard, specifically Annex H. Designed for AMD MPSoC, SoC, and FPGA, it excels in still image and video compression without sacrificing data integrity.<br><br>This IP core is instrumental in professional fields like medical imaging and security systems, where maintaining image quality during compression is crucial. It aligns well with applications requiring high compression fidelity, ensuring that all data details are retained during encoding.<br><br>The logiJPGE-LS encoder streamlines the creation of compressed video streams, enhancing data efficiency while preserving quality. It is indispensable in scenarios demanding precise image representation combined with optimal resource management.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
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