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All IPs > Interface Controller & PHY > AMBA AHB / APB/ AXI > eFPGA

eFPGA

From ADICSYS

Description

The eFPGA offering by ADICSYS provides a flexible and programmable solution that can be embedded within ASICs and SOCs. These soft FPGA IPs are fully synthesizable, offering RTL design flow compatibility that enables ease of use and integration with existing systems. The inherent flexibility of eFPGA allows for dynamic updates and enhancements post-production, addressing specification changes and offering significant reduction in development and design verification timelines.

Features
  • Dynamic configurability
  • Standard RTL friendly
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Class Value
Categories Interface Controller & PHY > AMBA AHB / APB/ AXI
Platform Level IP > Processor Core Independent
Platform Level IP > Multiprocessor / DSP
Synthesizable RTL Fully compatible with existing ASIC flows.
Custom Logic Capability Adaptable for various silicon design needs.
Availability All Countries & Regions
Applications
  • Silicon IPs
  • Custom ASIC designs
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