The eFPGA from ADICSYS is a versatile and customizable soft FPGA IP designed for seamless integration into ASICs and SOCs. This embedded FPGA technology is distinguished by its technology independence, allowing it to be incorporated into various standard RTL design flows without hassle. Companies can take advantage of the immediate access provided by ADICSYS to implement eFPGA directly into their projects.
The eFPGA IP is highly customizable, as companies can tailor it to specific dimensions, aspect ratios, and architectural parameters, such as the count and style of lookup tables and routing density. This customization capability ensures that the eFPGA can meet particular design constraints related to area, performance, and power requirements. Furthermore, ADICSYS provides the necessary Verilog programmable IP, which includes synthesizable RTL, constraint files, and their unique Acompile software for compilation.
In addition to supporting customers in the development phase, ADICSYS offers a bitstream loader and test program to facilitate the testing and integration of the eFPGA into final products. Designed to be delivered as both soft IP and, when necessary, as a hard block (in formats like GDSII, OpenAccess, or Milkyway), the eFPGA allows flexibility and extensive configurability for various high-tech applications.
