The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for better performance and efficiency as well as robust service availability. Features include irregular parity check matrix, layered decoding, minimum sum algorithm, and soft decision decoding. The BCH decoder works on GF(2^m) where m=16 or 14 and corrects up to t errors, with t being 8, 10, or 12. It is ETSI EN 302 307-1 V1.4.1 (2014-11) compliant. Other key features include medium codeword length, extra code rates for finer gradation, support for 64, 128, 256 APSK, and operation in very low SNR environments down to -10dB with wideband support. This results in improved performance, efficiency with respect to Shannon’s limit, finer gradation of code rate and SNR, and enables very high data rates and maximum service availability at highest efficiency, along with cross-layer optimization. Deliverables include synthesizable Verilog, system model in Matlab, Verilog test benches, and documentation. A comprehensive DVB-S2X Wideband LDPC/BCH decoder datasheet is available under NDA.
