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All IPs > Wireless Communication > Digital Video Broadcast > DVB-S2 LDPC/BCH Decoder and Encoder

DVB-S2 LDPC/BCH Decoder and Encoder

From Global IP Core Sales

Description

The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.

Deliverables
Soft IP
  • Synthesizable RTL
  • Verilog integration testbench
  • Sample simulation script
  • Datasheet
Features
  • Irregular parity check matrix
  • Layered Decoding
  • Minimum sum algorithm
  • Soft decision decoding
  • BCH decoder works on GF(2m)
  • ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
  • Long and short frame lengths
  • No error floor to QEF in Standard
  • Easy to integrate within receiver
  • All code rates and modulation orders
  • Wideband support
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Class Value
Categories Wireless Communication > Digital Video Broadcast
Wireline Communication > Modulation/Demodulation
Availability US, Canada, UK & EU Only
Applications
  • DVB-S2
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