All IPs > Interface Controller & PHY > USB > DSER12G
DSER12G is engineered for robust data and clock recovery, supporting data rates from 8.5 to 11.3Gb/s. It operates independently on data coding and offers deserialization in a 1:32 ratio. Tested on fiber optic transceiver ASICs, the IP utilizes IBM's 65nm 10LPe process to ensure low power operation and high performance in SONET/SDH OC-192 systems, making it a critical component in high-speed data transfer,
| Category | Interface Controller & PHY > USB |
| Process Node | 65nm |
| Availability | All Countries & Regions |
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