Overview:
The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting.
Key Features:
CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X
PCIe Compatibility: Supports PCIe spec 6.0/5.0
CPI Interface: Support for CPI Interface
AXI Interface: Configurable AXI master, AXI slave
Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16
Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode
Register Checks: Configuration and Memory Mapped registers
Dual Mode: Supports Dual Mode operation
Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers
CXL Support: Can function as both CXL host and device
Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers
FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass
Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)
Power Management: Supports Power Management features
Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD
Testing: Compliance Testing and Error Scenarios support
