The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time. Pipeline architecture is followed which significantly speeds up the whole decoding process. Also, layered architecture is implemented which helps to enhance the speed of the decoding process. AR4JA LDPC decoder supports soft decision decoding and hard decision output. Additional features include: CCSDS AR4JA LDPC Code family is quasi-cyclic, irregular parity check matrix, run time configuration for more than one code rate (i.e., 1/2, 2/3, 3/4), configurable codeword size that supports 2K, 3K, and 4K information words, minimum sum algorithm, and layered decoding architecture.
