The CAN 2.0/CAN FD controller is an advanced embedded solution designed for seamless integration into FPGAs and ASICs, supporting both standard CAN and the enhanced CAN FD protocol. This IP core complies fully with the ISO 11898-1:2015 standard, allowing payloads to achieve significantly higher transmission rates of up to 10 Mbit/s and expanding payload capacity to 64 bytes, compared to the traditional 8 bytes.
Designed for compatibility, this IP solution works with a wide range of FPGA devices from Xilinx, Altera, Lattice, and Microsemi. It natively supports system bus interfaces such as AXI, Avalon, and APB, ensuring flexible processor integration options that cater to SOC FPGA types. Its architecture is particularly beneficial for applications needing robust diagnostic and CAN bus debugging tools, making it well-suited for data loggers and similar devices.
Additional features of the CAN 2.0/CAN FD controller include low-latency DMA with interrupt rate adaptation, auto-acknowledge modes, single-shot capabilities, and configurable hardware buffer sizes. Designed with a small footprint, this IP core can be configured to minimize resource usage when advanced features are not required, offering a balanced solution for both traditional and modern applications.
