Avispado is crafted as a 64-bit in-order RISC-V core that prioritizes efficiency and simplicity. Designed for energy-sensitive systems, it provides a balance between performance and power consumption, making it ideal for machine learning tasks where energy efficiency is paramount. Its 2-wide in-order pipeline smoothly manages instruction processing while maintaining low power usage.
This core's architecture supports high-performance computing demands by allowing extensive customization, such as scalable instruction and data cache sizes and branch prediction tuning. Its integration with the Gazzillion Misses™ technology enhances its capacity to manage data with high sparsity, resulting in superior energy efficiency per operation. Its vector-ready design with the Vector Specification 1.0 provides flexibility in computational tasks, enhancing its workload handling capabilities.
Avispado is equipped for multiprocessing environments with support for cache coherence, leveraging the CHI interface and customizable down to AXI. This flexibility makes Avispado a perfect component for building cost-efficient, high-performance SoCs tailored for specific machine learning applications, providing robust performance without excessive silicon footprint.
