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All IPs > Interface Controller & PHY > AMBA AHB / APB/ AXI > AMBA AXI Target

AMBA AXI Target

From Agnisys, inc.

Description

The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.

Deliverables
Soft IP
  • Synthesizable RTL
  • Verilog integration testbench
  • Datasheet
  • Hardware user guide
  • IDesignSpec tool to configure
Features
  • Independent read and write channels
  • Multiple outstanding addresses on single ID
  • Support for unaligned data transfers
  • Out-of-order transaction completion
  • Burst transactions based on start address
  • Flopped and non-flopped
  • Synchronous or asynchronous reset type
  • AXI4 lite, AXI4 full, and AXI5 lite
  • Low Data Latency or wait stages
Tech Specs
Category Interface Controller & PHY > AMBA AHB / APB/ AXI
Availability All Countries & Regions
Applications
  • Mobile
  • AI
  • Autonomous Technology
  • Research & Science and Engineering Services
  • Military & Aerospace
  • Information & Technology
  • Semiconductor Industry
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