The CPU, or Central Processing Unit, is the central component of computer systems, acting as the brain that executes instructions and processes data. Our category of CPU semiconductor IPs offers a diverse selection of intellectual properties that enable the development of highly efficient and powerful processors for a wide array of applications, from consumer electronics to industrial systems. Semiconductor IPs in this category are designed to meet the needs of modern computing, offering adaptable and scalable solutions for different technology nodes and design requirements.
These CPU semiconductor IPs provide the core functionalities required for the development of processors capable of handling complex computations and multitasking operations. Whether you're developing systems for mobile devices, personal computers, or embedded systems, our IPs offer optimized solutions that cater to the varying demands of power consumption, processing speed, and operational efficiency. This ensures that you can deliver cutting-edge products that meet the market's evolving demands.
Within the CPU semiconductor IP category, you'll find a range of products including RISC (Reduced Instruction Set Computer) processors, multi-core processors, and customizable processor cores among others. Each product is designed to integrate seamlessly with other system components, offering enhanced compatibility and flexibility in system design. These IP solutions are developed with the latest architectural advancements and technological improvements to support next-generation computing needs.
Selecting the right CPU semiconductor IP is crucial for achieving target performance and efficiency in your applications. Our offerings are meticulously curated to provide comprehensive solutions that are robust, reliable, and capable of supporting diverse computing applications. Explore our CPU semiconductor IP portfolio to find the perfect components that will empower your innovative designs and propel your products into the forefront of technology.
The NMP-750 is a high-performance accelerator designed for edge computing, particularly suited for automotive, AR/VR, and telecommunications sectors. It boasts an impressive capacity of up to 16 TOPS and 16 MB local memory, powered by a RISC-V or Arm Cortex-R/A 32-bit CPU. The three AXI4 interfaces ensure seamless data transfer and processing. This advanced accelerator supports multifaceted applications such as mobility control, building automation, and multi-camera processing. It's designed to cope with the rigorous demands of modern digital and autonomous systems, offering substantial processing power and efficiency for intensive computational tasks. The NMP-750's ability to integrate into smart systems and manage spectral efficiency makes it crucial for communications and smart infrastructure management. It helps streamline operations, maintain effective energy management, and facilitate sophisticated AI-driven automation, ensuring that even the most complex data flows are handled efficiently.
The Tianqiao-70 CPU core by StarFive is a low-power RISC-V processor, designed specifically to address the needs of commercial applications that prioritize energy efficiency. This 64-bit CPU core is versatile, catering to various sectors including mobile devices, IoT applications, and intelligent consumer electronics that demand performance without compromising on power. Designed with efficient power utilization at its core, the Tianqiao-70 is tailored to offer high computation capacity while keeping energy consumption minimal, thereby extending device battery life and reducing operational costs. This processor core supports a vast spectrum of computational tasks while maintaining low-level power metrics, an essential factor in mobile and embedded applications. Through its effective design, the Tianqiao-70 continues to support a wide array of tasks efficiently, allowing businesses to lower their energy usage while achieving powerful processing capabilities. This core stands as an ideal solution for forward-thinking organizations that value sustainability and legacy support in their tech stack.
The KL730 AI SoC is powered by Kneron's innovative third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This architecture offers enhanced efficiency for the latest CNNnetwork architectures and serves transformer applications by reducing DDR bandwidth requirements significantly. The chip excels in video processing, supporting 4K 60FPS output and excelling in areas such as noise reduction and low-light imaging. It's ideal for applications in intelligent security, autonomous driving, and video conferencing, among others.
The Origin E1 is an optimized neural processing unit (NPU) targeting always-on applications in devices like home appliances, smartphones, and security cameras. It provides a compact, energy-efficient solution with performance tailored to 1 TOPS, making it ideal for systems needing low-power and minimal area. The architecture is built on Expedera's unique packet-based approach, which enables enhanced resource utilization and deterministic performance, significantly boosting efficiency while avoiding the pitfalls of traditional layer-based architectures. The architecture is fine-tuned to support standard and custom neural networks without requiring external memory, preserving privacy and ensuring fast processing. Its ability to process data in parallel across multiple layers results in predictive performance with low power and latency. Always-sensing cameras leveraging the Origin E1 can continuously analyze visual data, facilitating smoother and more intuitive user interactions. Successful field deployment in over 10 million devices highlights the Origin E1's reliability and effectiveness. Its flexible design allows for adjustments to meet the specific PPA requirements of diverse applications. Offered as Soft IP (RTL) or GDS, this engine is a blend of efficiency and capability, capitalizing on the full scope of Expedera's software tools and custom support features.
The AX45MP is engineered as a high-performance processor that supports multicore architecture and advanced data processing capabilities, particularly suitable for applications requiring extensive computational efficiency. Powered by the AndesCore processor line, it capitalizes on a multicore symmetric multiprocessing framework, integrating up to eight cores with robust L2 cache management. The AX45MP incorporates advanced features such as vector processing capabilities and support for MemBoost technology to maximize data throughput. It caters to high-demand applications including machine learning, digital signal processing, and complex algorithmic computations, ensuring data coherence and efficient power usage.
The Metis AIPU M.2 accelerator module by Axelera AI is engineered for AI inference on edge devices with power and budget constraints. It leverages the quad-core Metis AIPU, delivering exceptional AI processing in a compact form factor. This solution is ideal for a range of applications, including computer vision in constrained environments, providing robust support for multiple camera feeds and parallel neural networks. With its easy integration and the comprehensive Voyager SDK, it simplifies the deployment of advanced AI models, ensuring high prediction accuracy and efficiency. This module is optimized for NGFF (Next Generation Form Factor) M.2 sockets, boosting the capability of any processing system with modest space and power requirements.
The RV12 RISC-V Processor from Roa Logic is a highly adaptable, single-issue processor designed to comply with modern RISC-V standards, specifically targeting the embedded systems market. Structured around a 32-bit and 64-bit RISC-V instruction set, the processor employs a Harvard architecture to optimize the bandwidth of instruction and data accesses. It offers enhanced customization and configurability, allowing developers to adapt the processor for a variety of applications. This processor supports modular design approaches and can be efficiently integrated into both FPGA and ASIC designs, making it a versatile choice in the development of cutting-edge technologies. Its industry-standard compliance ensures ease of integration into existing systems that utilize RISC-V specifications, resulting in reduced development time and effort. As part of the broader RISC-V ecosystem promoted by Roa Logic, the RV12 boasts a robust architecture that facilitates experimental and commercial use, providing a solid foundation for innovation. Available for non-commercial purposes through a flexible licensing agreement, it supports the open movement towards collaborative digital innovation.
The A25 processor model is a versatile CPU suitable for a variety of embedded applications. With its 5-stage pipeline and 32/64-bit architecture, it delivers high performance even with a low gate count, which translates to efficiency in power-sensitive environments. The A25 is equipped with Andes Custom Extensions that enable tailored instruction sets for specific application accelerations. Supporting robust high-frequency operations, this model shines in its ability to manage data prefetching and cache coherence in multicore setups, making it adept at handling complex processing tasks within constrained spaces.
The NMP-350 is a cutting-edge endpoint accelerator designed to optimize power usage and reduce costs. It is ideal for markets like automotive, AIoT/sensors, and smart appliances. Its applications span from driver authentication and predictive maintenance to health monitoring. With a capacity of up to 1 TOPS and 1 MB of local memory, it incorporates a RISC-V/Arm Cortex-M 32-bit CPU and supports three AXI4 interfaces. This makes the NMP-350 a versatile component for various industrial applications, ensuring efficient performance and integration. Developed as a low-power solution, the NMP-350 is pivotal for applications requiring efficient processing power without inflating energy consumption. It is crucial for mobile and battery-operated devices where every watt conserved adds to the operational longevity of the product. This product aligns with modern demands for eco-friendly and cost-effective technologies, supporting enhanced performance in compact electronic devices. Technical specifications further define its role in the industry, exemplifying how it brings robust and scalable solutions to its users. Its adaptability across different applications, coupled with its cost-efficiency, makes it an indispensable tool for developers working on next-gen AI solutions. The NMP-350 is instrumental for developers looking to seamlessly incorporate AI capabilities into their designs without compromising on economy or efficiency.
Designed for high-demand applications in server and computing environments, the SCR9 Processor Core stands as a robust 64-bit RISC-V solution. It features a 12-stage superscalar, out-of-order pipeline to handle intensive processing tasks, further empowered by its versatile floating-point and vector processing units. The core is prepared to meet extensive computing needs with support for up to 16-core clustering and seamless AOSP or Linux operating systems integration.\n\nInvesting in powerful memory subsystems including L1, L2, and shared L3 caches enhances data handling, while features like memory coherency ensure fluid operation in multi-core settings. Extensions in cryptography and vector operations further diversify its application potential, establishing the SCR9 as an ideal candidate for cutting-edge data tasks.\n\nFrom enterprise servers to personal computing devices, video processing, and high-performance computations for AI and machine learning, the SCR9 delivers across an array of demanding scenarios. Its design integrates advanced power and process technologies to cater to complex computing landscapes, embodying efficiency and innovation in processor core technology.
The Origin E8 NPU by Expedera is engineered for the most demanding AI deployments such as automotive systems and data centers. Capable of delivering up to 128 TOPS per core and scalable to PetaOps with multiple cores, the E8 stands out for its high performance and efficient processing. Expedera's packet-based architecture allows for parallel execution across varying layers, optimizing resource utilization, and minimizing latency, even under strenuous conditions. The E8 handles complex AI models, including large language models (LLMs) and standard machine learning frameworks, without requiring significant hardware-specific changes. Its support extends to 8K resolutions and beyond, ensuring coverage for advanced visualization and high-resolution tasks. With its low deterministic latency and minimized DRAM bandwidth needs, the Origin E8 is especially suitable for high-performance, real-time applications. The high-speed processing and flexible deployment benefits make the Origin E8 a compelling choice for companies seeking robust and scalable AI infrastructure. Through customized architecture, it efficiently addresses the power, performance, and area considerations vital for next-generation AI technologies.
The eSi-3250 is a robust 32-bit processor core from eSi-RISC, specifically engineered to handle high-performance computing with extensive caching capabilities. It is particularly efficient when dealing with slower memory systems such as eFlash or off-chip alternatives, optimizing system throughput by leveraging its configurable instruction and data caches. This core supports a comprehensive instruction set, including optional application-specific instructions and standard floating-point operations compliant with IEEE standards. Its architecture makes use of 16 and 32-bit instructions to maximize code density, ensuring efficient use of cache and system resources. Designed with high clock speed potential, the eSi-3250 integrates a multi-mode MMU, allowing for complex memory management strategies. This core is exceptionally suitable for scenarios demanding high computational power within FPGA or ASIC implementations. It provides flexible integration options through its AMBA-compliant bus interfaces, supporting a vast range of ancillary IP modules to tailor performance to specific application needs.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Ventana's Veyron V2 CPU represents the pinnacle of high-performance AI and data center-class RISC-V processors. Engineered to deliver world-class performance, it supports extensive data center workloads, offering superior computational power and efficiency. The V2 model is particularly focused on accelerating AI and ML tasks, ensuring compute-intensive applications run seamlessly. Its design makes it an ideal choice for hyperscale, cloud, and edge computing solutions where performance is non-negotiable. This CPU is instrumental for companies aiming to scale with the latest in server-class technology.
The KL520 AI SoC is a groundbreaking chip that initiated Kneron's journey in edge AI. It is characterized by its compact size, energy efficiency, and robust performance, suitable for a host or companion AI co-processor role. Compatible with multiple 3D sensor technologies, the KL520 excels in smart home applications like smart locks and cameras. Its small power footprint allows operations on simple power supplies like AA batteries, setting it apart in the market.
AndesCore Processors offer a robust lineup of high-performance CPUs tailored for diverse market segments. Employing the AndeStar V5 instruction set architecture, these cores uniformly support the RISC-V technology. The processor family is classified into different series, including the Compact, 25-Series, 27-Series, 40-Series, and 60-Series, each featuring unique architectural advances. For instance, the Compact Series specializes in delivering compact, power-efficient processing, while the 60-Series is optimized for high-performance out-of-order execution. Additionally, AndesCore processors extend customization through Andes Custom Extension, which allows users to define specific instructions to accelerate application-specific tasks, offering a significant edge in design flexibility and processing efficiency.
Designed for embedded control applications, the eSi-3200 is a high-performing 32-bit processor core. It offers a balance of low-cost implementation and significant processing capability, making it a fitting choice for environments necessitating efficient on-chip memory usage. The eSi-3200 leverages a cacheless architecture that ensures deterministic computation, ideal for real-time systems. Its comprehensive instruction set includes advanced arithmetic operations and optional IEEE 754 compliant single-precision floating-point instructions. This architecture enhances code density and minimizes power consumption via a mix of 16 and 32-bit instructions. With a 5-stage pipeline, this core can achieve high clock speeds, enhancing its utility in demanding applications. It accommodates both user and supervisor modes for secure operation and supports extensive hardware debugging features to streamline development and troubleshooting processes. The eSi-3200 also facilitates integration through AMBA bus compatibility, enabling connectivity with a wide variety of peripheral IPs.
The eSi-1600 is a compact 16-bit RISC processor core engineered for efficiency and low power. It is well-suited for control applications that typically utilize 8-bit systems, boasting reduced system costs akin to those smaller CPUs, yet providing significantly higher performance. Its architecture allows for reduced clock cycles per application, resulting in substantial power savings, which is particularly beneficial in resource-constrained environments. This processor core features a 5-stage pipeline that enhances its ability to achieve higher clock frequencies, even in matured semiconductor processes. It includes a rich set of arithmetic instructions, offering capabilities like full 32-bit multiplication and accumulations, bit manipulation, and optional application-specific instructions. This versatility is further illustrated by the optional support for user and supervisor operating modes, reflecting its adaptability across multiple application scenarios. Besides typical features such as JTAG or serial debug capabilities, the eSi-1600 supports a wide array of peripherals through standard AMBA interconnects. Its instruction set achieves exceptional code density by utilizing intermixed 16 and 32-bit instructions. The processor's silicon-proven design, combined with extensive toolchain support, makes it a highly reliable choice for low-cost embedded applications.
The Chimera GPNPU is a general-purpose neural processing unit designed to address key challenges faced by system on chip (SoC) developers when deploying machine learning (ML) inference solutions. It boasts a unified processor architecture capable of executing matrix, vector, and scalar operations within a single pipeline. This architecture integrates the functions of a neural processing unit (NPU), digital signal processor (DSP), and other processors, which significantly simplifies code development and hardware integration. The Chimera GPNPU can manage various ML networks, including classical frameworks, vision transformers, and large language models, all within a single processor framework. Its flexibility allows developers to optimize performance across different applications, from mobile devices to automotive systems. The GPNPU family is fully synthesizable, making it adaptable to a range of performance requirements and process technologies, ensuring long-term viability and adaptability to changing ML workloads. The Cortex's sophisticated design includes a hybrid Von Neumann and 2D SIMD matrix architecture, predictive power management, and sophisticated memory optimization techniques, including an L2 cache. These features help reduce power usage and enhance performance by enabling the processor to efficiently handle complex neural network computations and DSP algorithms. By merging the best qualities of NPUs and DSPs, the Chimera GPNPU establishes a new benchmark for performance in AI processing.
The NMP-550 is tailored for enhanced performance efficiency, serving sectors like automotive, mobile, AR/VR, drones, and robotics. It supports applications such as driver monitoring, image/video analytics, and security surveillance. With a capacity of up to 6 TOPS and 6 MB local memory, this accelerator leverages either a RISC-V or Arm Cortex-M/A 32-bit CPU. Its three AXI4 interface support ensures robust interconnections and data flow. This performance boost makes the NMP-550 exceptionally suited for devices requiring high-frequency AI computations. Typical use cases include industrial surveillance and smart robotics, where precise and fast data analysis is critical. The NMP-550 offers a blend of high computational power and energy efficiency, facilitating complex AI tasks like video super-resolution and fleet management. Its architecture supports modern digital ecosystems, paving the way for new digital experiences through reliable and efficient data processing capabilities. By addressing the needs of modern AI workloads, the NMP-550 stands as a significant upgrade for those needing robust processing power in compact form factors.
The RISC-V Core-hub Generators are sophisticated tools designed to empower developers with complete control over their processor configurations. These generators allow users to customize their core-hubs at both the Instruction Set Architecture (ISA) and microarchitecture levels, offering unparalleled flexibility and adaptability in design. Such capabilities enable fine-tuning of processor specifications to meet specific application needs, fostering innovation within the RISC-V ecosystem. By leveraging the Core-hub Generators, developers can streamline their chip design process, ensuring efficient and seamless integration of custom features. This toolset not only simplifies the design process but also reduces time-to-silicon, making it ideal for industries seeking rapid advancements in their technological capabilities. The user-friendly interface and robust support of these generators make them a preferred choice for developing cutting-edge processors. InCore Semiconductors’ RISC-V Core-hub Generators represent a significant leap forward in processor design technology, emphasizing ease of use, cost-effectiveness, and scalability. As demand for tailored and efficient processors grows, these generators are set to play a pivotal role in shaping the future of semiconductor design, driving innovation across multiple sectors.
xcore.ai is a versatile platform specifically crafted for the intelligent IoT market. It hosts a unique architecture with multi-threading and multi-core capabilities, ensuring low latency and high deterministic performance in embedded AI applications. Each xcore.ai chip contains 16 logical cores organized in two multi-threaded processor 'tiles' equipped with 512kB of SRAM and a vector unit for enhanced computation, enabling both integer and floating-point operations. The design accommodates extensive communication infrastructure within and across xcore.ai systems, providing scalability for complex deployments. Integrated with embedded PHYs for MIPI, USB, and LPDDR, xcore.ai is capable of handling a diverse range of application-specific interfaces. Leveraging its flexibility in software-defined I/O, xcore.ai offers robust support for AI, DSP, and control processing tasks, making it an ideal choice for enhancing IoT device functionalities. With its support for FreeRTOS, C/C++ development environment, and capability for deterministic processing, xcore.ai guarantees precision in performance. This allows developers to partition xcore.ai threads optimally for handling I/O, control, DSP, and AI/ML tasks, aligning perfectly with the specific demands of various applications. Additionally, the platform's power optimization through scalable tile clock frequency adjustment ensures cost-effective and energy-efficient IoT solutions.
The NaviSoC is a cutting-edge system-on-chip (SoC) that integrates a GNSS receiver and an application processor on one silicon die. Known for its high precision and reliability, it provides users with a compact and energy-efficient solution for various applications. Capable of supporting all GNSS bands and constellations, it offers fast time-to-first-fix, centimeter-level accuracy, and maintains high sensitivity even in challenging environments. The NaviSoC's flexible design allows it to be customized to meet specific user requirements, making it suitable for a wide range of applications, from location-based services to asset tracking and smart agriculture. The incorporation of a RISC-V application microcontroller, along with an array of peripherals and interfaces, introduces expanded functionality, optimizing it for advanced IoT and industrial applications. Engineered for power efficiency, the NaviSoC supports a range of supply voltages, ensuring low power consumption across its operations. The chip's design provides for efficient integration into existing systems with the support of a comprehensive SDK and IDE, allowing developers to tailor solutions to their precise needs in embedded systems and navigation infrastructures.
Standing at the pinnacle of eSi-RISC's processor cores, the eSi-3264 offers a powerful 32/64-bit architecture with DSP extensions designed for intensive computing tasks. Its unique ability to process both SIMD fixed and floating-point operations makes it ideal for advanced applications requiring complex digital signal processing with minimal hardware footprint. The eSi-3264 excels in applications needing DSP capabilities due to its fully pipelined MAC unit and the support for dual and quad 64-bit accumulations. The architecture supports a wide range of application-specific instructions and enhanced memory management via configurable caches and an optional MMU. Leveraging industry-standard interfaces, it allows seamless integration with existing chip architectures. These capabilities, coupled with high code density and efficient power management strategies, reinforce its suitability for next-generation multimedia, signal processing, and control systems looking to maximize performance and minimize power consumption.
The KL630 AI SoC introduces state-of-the-art NPU architecture, being the first to support both Int4 precision and transformer neural networks. It offers notable energy efficiency and is built on the ARM Cortex A5 CPU, providing up to 1eTOPS@int4. The KL630 supports various AI frameworks, making it suitable for a wide array of edge AI devices and applications that require advanced ISP capabilities and 5M@30FPS HDR imaging.
The Y180 is a streamlined microprocessor design, incorporating approximately 8K gates and serving primarily as a CPU clone of the Zilog Z180. It caters to applications requiring efficient, compact processing power without extensive resource demands. Its design is particularly apt for systems that benefit from Z80 architecture compatibility, ensuring effortless integration and functionality within a variety of technological landscapes.
The Yitian 710 Processor stands as a flagship ARM-based server processor spearheaded by T-Head, featuring an intricate architecture designed by the company itself. Utilizing advanced multi-core technology, the processor incorporates up to 128 high-performance ARMv9 CPU cores, each complete with its own substantial cache for enhanced data access speed. The processor is adeptly configured to handle intensive computing tasks, supported by a robust off-chip memory system with 8-channel DDR5, reaching peak bandwidths up to 281GB/s. An impressive I/O subsystem featuring PCIe 5.0 interfaces facilitates extensive data throughput capabilities, making it highly suitable for high-demand applications. Compliant with modern energy efficiency standards, the processor boasts innovative multi-die packaging to maintain optimal heat dissipation, ensuring uninterrupted performance in data centers. This processor excels in cloud services, big data computations, video processing, and AI inference operations, offering the speed and efficiency required for next-generation technological challenges.
Expedera's Origin E6 NPU is crafted to enhance AI processing capabilities in cutting-edge devices such as smartphones, AR/VR headsets, and automotive systems. It offers scalable performance from 16 to 32 TOPS, adaptable to various power and performance needs. The E6 leverages Expedera's packet-based architecture, known for its highly efficient execution of AI tasks, enabling parallel processing across multiple workloads. This results in better resource management and higher performance predictability. Focusing on both traditional and new AI networks, Origin E6 supports large language models as well as complex data processing tasks without requiring additional hardware optimizations. Its comprehensive software stack, based on TVM, simplifies the integration of trained models into practical applications, providing seamless support for mainstream frameworks and quantization options. Origin E6's deployment reflects meticulous engineering, optimizing memory usage and processing latency for optimal functionality. It is designed to tackle challenging AI applications in a variety of demanding environments, ensuring consistent high-performance outputs and maintaining superior energy efficiency for next-generation technologies.
The SCR7 Application Core is an epitome of advanced data processing capability within the RISC-V framework, designed to handle the computational requirements of sophisticated applications. This Linux-capable 64-bit core incorporates a dual-issue, out-of-order 12-stage pipeline featuring vector and cryptography extensions, optimizing operations for heavy data-centric workloads.\n\nIts memory subsystem includes robust L1, L2, and MMU configurations that equip the SCR7 with the prerequisite tools for expansive architectural frameworks. Support for dual-core multiprocessor configurations and efficient cache coherency ensures streamlined operations, catering to diverse processing needs across networked and AI applications.\n\nApplications in high-performance computing, AI, and networking thrive with the SCR7 core's energy-efficient, data-allied design. From video processing to computer vision, this core empowers developers to transcend traditional limitations, ushering in a new era of computational capability for enterprise and consumer technologies alike.
The Origin E2 from Expedera is engineered to perform AI inference with a balanced approach, excelling under power and area constraints. This IP is strategically designed for devices ranging from smartphones to edge nodes, providing up to 20 TOPS performance. It features a packet-based architecture that enables parallel execution across layers, improving resource utilization and performance consistency. The engine supports a wide variety of neural networks, including transformers and custom networks, ensuring compatibility with the latest AI advancements. Origin E2 caters to high-resolution video and audio processing up to 4K, and is renowned for its low latency and enhanced performance. Its efficient structure keeps power consumption down, helping devices run demanding AI tasks more effectively than with conventional NPUs. This architecture ensures a sustainable reduction in the dark silicon effect while maintaining high operating efficiencies and accuracy thanks to its TVM-based software support. Deployed successfully in numerous smart devices, the Origin E2 guarantees power efficiency sustained at 18 TOPS/W. Its ability to deliver exceptional quality across diverse applications makes it a preferred choice for manufacturers seeking robust, energy-conscious solutions.
The Ultra-Low-Power 64-Bit RISC-V Core developed by Micro Magic, Inc. is a highly efficient processor designed to deliver robust performance while maintaining minimal power consumption. This core operates at a remarkable 5GHz frequency while consuming only 10mW of power at 1GHz, making it an ideal solution for applications where energy efficiency is critical. The design leverages innovative techniques to sustain high performance with low voltage operation, ensuring that it can handle demanding processing tasks with reliability. This RISC-V core showcases Micro Magic's expertise in providing high-speed silicon solutions without compromising on power efficiency. It is particularly suited for applications that require both computational prowess and energy conservation, making it an optimal choice for modern SoC (System-on-Chip) designs. The core's architecture is crafted to support a wide range of high-performance computing requirements, offering flexibility and adaptability across various applications and industries. Its integration into larger systems can significantly enhance the overall energy efficiency and speed of electronic devices, contributing to advanced technological innovations.
The Veyron V1 CPU is designed to meet the demanding needs of data center workloads. Optimized for robust performance and efficiency, it handles a variety of tasks with precision. Utilizing RISC-V open architecture, the Veyron V1 is easily integrated into custom high-performance solutions. It aims to support the next-generation data center architectures, promising seamless scalability for various applications. The CPU is crafted to compete effectively against ARM and x86 data center CPUs, providing the same class-leading performance with added flexibility for bespoke integrations.
The RISC-V Hardware-Assisted Verification by Bluespec is designed to expedite the verification process for RISC-V cores. This platform supports both ISA and system-level testing, adding robust features such as verifying standard and custom ISA extensions along with accelerators. Moreover, it offers scalable access through the AWS cloud, making verification available anytime and anywhere. This tool aligns with the needs of modern developers, ensuring thorough testing within a flexible and accessible framework.
The Avispado is a sleek and efficient 64-bit RISC-V in-order processing core tailored for applications where energy efficiency is key. It supports a 2-wide in-order issue, emphasizing minimal area and power consumption, which makes it ideal for energy-conscious system-on-chip designs. The core is equipped with direct support for unaligned memory accesses and is multiprocessor-ready, providing a versatile solution for modern AI needs. With its small footprint, Avispado is perfect for machine learning systems requiring little energy per operation. This core is fully compatible with RISC-V Vector Specification 1.0, interfacing seamlessly with Semidynamics' vector units to support vector instructions that enhance computational efficiency. The integration with Gazzillion Misses™ technology allows support for extensive memory latency workloads, ideal for key applications in data center machine learning and recommendation systems. The Avispado also features a robust set of RISC-V instruction set extensions for added capability and operates smoothly within Linux environments due to comprehensive memory management unit support. Multiprocessor-ready design ensures flexibility in embedding many Avispado cores into high-bandwidth systems, facilitating powerful and efficient processing architectures.
NeuroMosAIc Studio is a comprehensive software platform designed to maximize AI processor utilization through intuitive model conversion, mapping, simulation, and profiling. This advanced software suite supports Edge AI models by optimizing them for specific application needs. It offers precision analysis, network compression, and quantization tools to streamline the process of deploying AI models across diverse hardware setups. The platform is notably adept at integrating multiple AI functions and facilitating edge training processes. With tools like the NMP Compiler and Simulator, it allows developers to optimize functions at different stages, from quantization to training. The Studio's versatility is crucial for developers seeking to enhance AI solutions through customized model adjustments and optimization, ensuring high performance across AI systems. NeuroMosAIc Studio is particularly valuable for its edge training support and comprehensive optimization capabilities, paving the way for efficient AI deployment in various sectors. It offers a robust toolkit for AI model developers aiming to extract the maximum performance from hardware in dynamic environments.
aiWare stands out as a premier hardware IP for high-performance neural processing, tailored for complex automotive AI applications. By offering exceptional efficiency and scalability, aiWare empowers automotive systems to harness the full power of neural networks across a wide variety of functions, from Advanced Driver Assistance Systems (ADAS) to fully autonomous driving platforms. It boasts an innovative architecture optimized for both performance and energy efficiency, making it capable of handling the rigorous demands of next-generation AI workloads. The aiWare hardware features an NPU designed to achieve up to 256 Effective Tera Operations Per Second (TOPS), delivering high performance at significantly lower power. This is made possible through a thoughtfully engineered dataflow and memory architecture that minimizes the need for external memory bandwidth, thus enhancing processing speed and reducing energy consumption. The design ensures that aiWare can operate efficiently across a broad range of conditions, maintaining its edge in both small and large-scale applications. A key advantage of aiWare is its compatibility with aiMotive's aiDrive software, facilitating seamless integration and optimizing neural network configurations for automotive production environments. aiWare's development emphasizes strong support for AI algorithms, ensuring robust performance in diverse applications, from edge processing in sensor nodes to high central computational capacity. This makes aiWare a critical component in deploying advanced, scalable automotive AI solutions, designed specifically to meet the safety and performance standards required in modern vehicles.
The Dynamic Neural Accelerator II (DNA-II) is an advanced IP core that elevates neural processing capabilities for edge AI applications. It is adaptable to various systems, exhibiting remarkable efficiency through its runtime reconfigurable interconnects, which aid in managing both transformer and convolutional neural networks. Designed for scalability, DNA-II supports numerous applications ranging from 1k MACs to extensive SoC implementations. DNA-II's architecture enables optimal parallelism by dynamically managing data paths between compute units, ensuring minimized on-chip memory bandwidth and maximizing operational efficiency. Paired with the MERA software stack, it provides seamless integration and optimization of neural network tasks, significantly enhancing computation ordering and resource distribution. Its applicability extends across various industry demands, massively increasing the operational efficiency of AI tasks at the edge. DNA-II, the pivotal force in the SAKURA-II Accelerator, brings innovative processing strength in compact formats, driving forward the development of edge-based generative AI and other demanding applications.
The SCR1 Microcontroller Core is a 32-bit, open-source design that caters to entry-level and deeply embedded applications. This RISC-V-compatible core is crafted for general-purpose and control systems and features a 4-stage in-order pipeline with optional extensions for reduced base integer and integer multiplication and division. Robust interrupt handling and compatibility with industry-standard interfaces like AXI4, AHB-Lite, and JTAG make the SCR1 versatile for real-time applications. Its open-source stature under a permissive license offers both academic and commercial deployment opportunities right out of the box.\n\nAccompanying the SCR1 core is a comprehensive software package that includes pre-configured development tools to expedite deployment. Ready-made interactive development environments, such as Eclipse and Visual Studio Code, alongside standardized compilers, enable developers to harness the core's capabilities efficiently. A variety of simulators and debuggers streamline integration and testing processes, ensuring this core is not just powerful, but developer-friendly too.\n\nApplications for the SCR1 span across IoT, smart home solutions, as well as education programs, where its cost-effective, low-power design is highly advantageous. With capabilities suitable for smart cards, sensors, and various control systems, the SCR1 Microcontroller Core is a pivotal component in embedded systems, offering unparalleled flexibility and efficiency.
The eSi-1650 is an advanced 16-bit RISC processor core that incorporates an instruction cache for enhanced performance. Targeted at low-power applications traditionally serviced by 8-bit processors, the inclusion of caching makes the eSi-1650 especially effective when using non-volatile memories like Flash. The processor's power efficiency is emphasized through a low gate count and caches, which optimize the speed and power consumption when interfacing with slow memory technologies. This RISC core also supports a rich suite of instructions including full 32-bit mathematical operations and various user-defined instructions, providing crisp, responsive performance for embedded systems. Additional features include a configurable pipeline, vector interrupts, and compatibility with various AMBA buses, making integration with existing systems straightforward. The processor supports both dedicated user and supervisor operating modes, reflecting its flexibility and security considerations in professional applications.
Hanguang 800 AI Accelerator is a revolutionary AI processing powerhouse designed by T-Head to maximize computational efficiency for artificial intelligence applications. By leveraging state-of-the-art chip design, it achieves unparalleled processing speeds, significantly reducing inference times for machine learning tasks. Its architecture supports intricate AI algorithms adeptly, allowing for swift model training and execution across billions of parameters. Optimized for neural network operations, the accelerator adeptly caters to dense mathematical computations with minimal power consumption. Incorporating adaptive learning mechanisms, it autonomously refines its processing strategies in real-time, catalyzing efficiency gains. This is complemented by an advanced cooling system that manages thermal output without compromising computational power. Hanguang 800's application spectrum is broad, encompassing cloud-based AI services, edge computing, and embedded AI solutions in devices, positioning it as an ideal solution for industries demanding high-speed and scalable AI processing capabilities. Its integration into T-Head's ecosystem underscores the company’s commitment to delivering top-tier performance hardware for next-gen intelligent systems.
The Tyr Superchip is engineered to tackle the most daunting computational challenges in edge AI, autonomous driving, and decentralized AIoT applications. It merges AI and DSP functionalities into a single, unified processing unit capable of real-time data management and processing. This all-encompassing chip solution handles vast amounts of sensor data necessary for complete autonomous driving and supports rapid AI computing at the edge. One of the key challenges it addresses is providing massive compute power combined with low-latency outputs, achieving what traditional architectures cannot in terms of energy efficiency and speed. Tyr chips are surrounded by robust safety protocols, being ISO26262 and ASIL-D ready, making them ideally suited for the critical standards required in automotive systems. Designed with high programmability, the Tyr Superchip accommodates the fast-evolving needs of AI algorithms and supports modern software-defined vehicles. Its low power consumption, under 50W for higher-end tasks, paired with a small silicon footprint, ensures it meets eco-friendly demands while staying cost-effective. VSORA’s Superchip is a testament to their innovative prowess, promising unmatched efficiency in processing real-time data streams. By providing both power and processing agility, it effectively supports the future of mobility and AI-driven automation, reinforcing VSORA’s position as a forward-thinking leader in semiconductor technology.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The SCR6 Microcontroller Core is infused with high-performance attributes, optimizing operations for embedded RTOS applications requiring significant computational vigor. This silicon-proven, 64-bit RISC-V processor utilizes a 12-stage superscalar pipeline with out-of-order processing, enabling efficient execution of complex tasks. Complementing its high-precision floating-point unit are innovative cryptographic and bit manipulation extensions, broadening its functional scope across various domains.\n\nThis core supports multicore configurations accommodating up to 8 processors, alongside caches and a PMP unit that validate RTOS functionality. Standard interfaces like AXI4 and JTAG enrich its adaptability for embedded integrations, ensuring compatibility with evolving technology landscapes.\n\nDevelopers in industrial automation, motor control, image processing, and automotive systems benefit from the SCR6’s substantial computational capabilities. Its holistic design caters to advanced smart home and sensor fusion systems, delivering robust power and performance in an efficient, scalable format.
The SAKURA-II AI Accelerator stands out as a high-performance, energy-efficient edge co-processor designed to handle advanced AI tasks. Tailored for real-time, batch-one AI inferencing, it supports multi-billion parameter models, such as Llama 2 and Stable Diffusion, while maintaining low power consumption. The core technology leverages a dynamic neural accelerator for runtime reconfigurability and exceptional parallel processing, making it ideal for edge-based generative AI applications. With its flexible architecture, SAKURA-II facilitates the seamless execution of diverse AI models concurrently, without compromising on efficiency or speed. Integrated with the MERA compiler framework, it ensures easy deployment across various hardware systems, supporting frameworks like PyTorch and TensorFlow Lite for seamless integration. This AI accelerator excels in AI models for vision, language, and audio, fostering innovative content creation across these domains. Moreover, SAKURA-II supports a robust DRAM bandwidth, far surpassing competitors, ensuring superior performance for large language and vision models. It offers support for significant neural network demands, making it a powerful asset for developers in the edge AI landscape.
The SiFive Essential family of processors caters to a wide range of applications with its highly customizable IP cores. Designed to meet specific market needs, these processors range from small, power-efficient designs for microcontrollers to fully-featured, Linux-capable superscalar processors. Featuring configurable microarchitectures, the Essential family provides scalability in performance and power, making it an ideal choice for diverse applications from IoT to real-time control. The Essential series is highly adaptable, with series like the 2-Series offering power and area optimization through a 2-4 stage pipeline for embedded solutions. In contrast, the 6-Series and 7-Series provide extensive configurability with their 8-stage pipelines suited for more demanding applications requiring 32/64-bit capable systems. Emphasizing flexibility, the Essential family enables a mix-and-match capability, allowing designers to combine deterministic real-time processors with higher performance application cores. With built-in Trace + Debug capabilities and open-soc security features, the Essential processors provide an integrated solution for efficient and secure processing.
Designed with adaptability in mind, the FPGA-Modul Artix 7A100T-2C leverages the ARTIX-7 FPGA series from AMD to provide a powerful platform for a variety of applications. Its compact size does not compromise on performance or flexibility, making it suitable for both consumer and industrial applications, ranging from data processing to control systems. The module is equipped with essential components such as SDRAM and Flash memory, facilitating rapid data access and reliable storage options. The FPGA itself provides ample logic cells and DSP slices, allowing it to handle complex computing tasks effectively. These features enable developers to design and implement intricate logic and processing tasks directly on the module. With a rich set of I/O options, the Artix 7A100T-2C is capable of interfacing with numerous peripherals, offering a high degree of integration into existing systems. Its architecture is optimized for low power consumption while maintaining high speed and efficiency, making it suitable for battery-operated or power-sensitive applications.
The General Purpose Accelerator (Aptos) from Ascenium stands out as a redefining force in the realm of CPU technology. It seeks to overcome the limitations of traditional CPUs by providing a solution that tackles both performance inefficiencies and high energy demands. Leveraging compiler-driven architecture, this accelerator introduces a novel approach by simplifying CPU operations, making it exceptionally suited for handling generic code. Notably, it offers compatibility with the LLVM compiler, ensuring a wide range of applications can be adapted seamlessly without rewrites. The Aptos excels in performance by embracing a highly parallel yet simplified CPU framework that significantly boosts efficiency, reportedly achieving up to four times the performance of cutting-edge CPUs. Such advancements cater not only to performance-oriented tasks but also substantially mitigate energy consumption, providing a dual benefit of cost efficiency and reduced environmental impact. This makes Aptos a valuable asset for data centers seeking to optimize their energy footprint while enhancing computational capabilities. Additionally, the Aptos architecture supports efficient code execution by resolving tasks predominantly at compile-time, allowing the processor to handle workloads more effectively. This allows standard high-level language software to run with improved efficiency across diverse computing environments, aligning with an overarching goal of greener computing. By maximizing operational efficiency and reducing carbon emissions, Aptos propels Ascenium into a leading position in the sustainable and high-performance computing sector.
The Codasip RISC-V BK Core Series represents a lineup of processor cores that leverage the open standard architecture of RISC-V to deliver highly customizable computational solutions. These cores provide a balance between power efficiency and performance, making them ideal for a broad range of applications, including IoT devices and embedded systems. The BK series cores are designed to be versatile, supporting a variety of operating systems while allowing full customization to meet specific workload demands. This flexibility empowers designers to implement custom instructions and optimize the cores for particular applications without compromising on power budgets. The series is compliant with RISC-V standards, ensuring seamless integration with other RISC-V based solutions.
Equipped with a new NPU architecture, the KL530 AI SoC stands out as a versatile chip supporting INT4 precision and transformers with remarkable efficiency. Designed for low-power consumption, it attains up to 1 TOPS@INT4 while maintaining high processing efficiency. Its smart ISP enhances image quality through AI inference. The KL530 is ideal for AIoT applications and multimedia processing, providing high-efficiency compression with less than 500 ms cold start time.
The Rabbit 4000 microprocessor represents a significant escalation in processing capabilities, boasting an impressive 161K gate design and 128-pin configuration. Developed to cater to demanding digital environments, this processor delivers advanced performance alongside flexible deployment options. It is particularly tailored for use in complex systems requiring both potent processing power and diverse interface options, while still adhering to industry standards for adaptability and integration.
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