The AES Crypto IP Core from Dillon Engineering is a comprehensive solution adhering to the Advanced Encryption Standard (AES), as specified by FIPS 197. This core offers adaptability for both encryption and decryption tasks, supported by multiple operation modes such as ECB, CBC, CFB, OFB, and CTR.
Developed using the ParaCore Architect utility, this core is flexible in its application, easily customizable to meet specific performance or area requirements. It ensures high data throughput up to 12.8 Gb/s with several configurations available to balance throughput against silicon area in FPGA or ASIC implementations.
The IP supports dynamic key changes without impacting throughput, providing an effective balance of security and performance. It is available in both generic HDL and targeted EDIF formats, ensuring seamless integration within a range of project frameworks, equipped with a full testbench for validation.
